Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.atnf.csiro.au/people/Paul.Roberts/sestsam.pdf Дата изменения: Tue Jul 28 08:44:13 1998 Дата индексирования: Sat Dec 22 08:35:26 2007 Кодировка:

Australia Telescope National Facility
SEST SAMPLER Preliminary

Paul Roberts 16 July 1998 1.0 Introduction
The ATNF SEST sampler is a wideband, two-bit, three-level sampler operating at up to 2.048 Giga-samples per second for use with the ATNF SEST correlator. The function of the sampler is to sample and digitise an input IF passband of up to 1.024 GHz bandwidth and convert the data into a format compatible with the ATNF SEST correlator. Another key function of the sampler is to maintain the digitising thresholds at the optimum value for a three-level correlator to maintain maximum signal to noise ratio.

2.0 Physical Desciption
The sampler is housed in a 17" x 2U rack case. Inputs to the sampler consist of: 1) The input IF at an rms power level of ~0dBm at all bandwidths entering on a single rear bulkhead SMA connector. 2) A differential ECL clock at the sample rate entering on two rear bulkhead SMA connectors. Data output from the sampler is 16 sample wide, 32 pair balanced ECL, physically consisting of two 34 way cables with 16 data signals and one clock in each cable. The clock is at half the output data rate with rising and falling edges aligned with the output data. Physical connection with the sampler is via two 37 pin female D type connectors. Communication with the sampler is via a standard ATNF Interface card (16 bit parallel multiplexed address/data bus) from the correlator block control computer. The interface connects to the sampler via a 26 pin female high density D type connector. In addition an RS-232 serial port is provided for auxillary communications or status display on a serial terminal. The serial port connects to the sampler via a 9 pin female D type connector.The is also an output display port which drives a front panel 2 line by 20 character alphanumeric display. The sampler physically consists of four sections: 1) The high speed buffer amplifier/comparater. This consists of a wideband buffer amplifier followed by a power spitter and dual high-speed comparator integrated onto a high dielectric constant substrate with 1/4 inch copper base. This section is contained within its own RF tight enclosure with the output ECL data exiting via small diameter (0.9mm) semi-rigid coax. This section is mechanically fixed to the high speed ECL board.


2) The high speed ECL board. This board latches the data from the comparators at up to 2.048 GS/s and performs a 1:4 serial to parallel conversion of the sampled data. 3) The medium speed ECL board. This board takes the 4 sample wide data from the high speed ECL board at speeds up to 512 MS/s and performs a further 1:4 serial to parallel conversion of the sampled data to give a final 16 sample wide data output to the correlator. This board also counts the number of samples in the outer quantisation levels and passes this to the control board to allow automatic control of the sampler threshold levels. This board is designed to operate at up to 1.024 GS/s to allow for future upgrade to wider bandwidths. 4) The control board. This board uses the outputs of the ripple counters on the medium speed ECL board to determine the statistics of the sampled data and from this control the sampler threshold levels with a real time digital feedback loop. This board also implements the sampler external communication interface via a standard ATNF Interface port, RS-232 serial port and front panel alphanumeric display port. The funtionality of the board is provided by an on board DSP processor and high density FPGA. The ampifier/comparator, high speed ECL board and medium speed ECL board are all contained within an RF tight enclosure for maximum RFI immunity. Connection to the control board is via a 26 pin high density female D type connector for the digital control signals and two semi-rigid coaxial lines for the sampler threshold levels.

3.0 Electrical Description
3.1 High Speed ECL Board
RESET 2 2 2 2 2 2 2 2 2 2

LEVEL

VCC

VTT

VEE

ERR

15V

S/P IF Amp/Comparator S/P

D0 D1 D2 D3 CLK D0 D1 D2 D3 CLK

CLOCK

2

Figure 1. High Speed ECL Board 3.1.1 Signal Description Signal IF CLOCK D0-3 CLK ERR Type Analogue @ 0 dBm Differential ECL Differential ECL Differential ECL TTL Description Analogue input Sample clock at up to 2.048 GHz Output data. D0 oldest sample Data clock at the output data rate (i.e. CLOCK/4) S/P converters out of sync error


RESET 10K ECL Reset S/P converters and sync detection circuit Table 1. High speed ECL board signal description 3.2 Medium Speed ECL Board
TO CONTROL BOARD 6 CONTROL

9 COUNTS

J1 26PIN FROM HIGH SPEED ECL BOARD OUTPUT DATA LATCHES J2 37PIN BIT0 D0..3 8 SAMPLE COUNTERS S/P CONVERTERS CLK 2 I/O CHIPS 32 D0..7 2 CLOCK TO CORRELATOR

2 TEMP

CLK

2

J3 37PIN

BIT1 D0..3 8

SYNC DETECTOR

32 D8..15

2

CLOCK

Figure 2. Medium speed ECL board 3.2.1 Signal Description Connector J1 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Type O O O O O O O O O O O I I I I I I/O Name COUNTA1 COUNTA2 COUNTA3 COUNTA4 COUNTB1 COUNTB2 COUNTB3 COUNTB4 CLKCOUNT SYNCERR0 SYNCERR1 GRESET0 GRESET1 CRESET CLENAB TCLK TDATA Function (All signals TTL levels) Sample counter D7 output Sample counter D7 output Sample counter D7 output Sample counter D7 output Sample counter D7 output Sample counter D7 output Sample counter D7 output Sample counter D7 output Clock counter D7 output S/P converter Sync error on high speed ECL board S/P converter Sync error on medium speed ECL board Reset high speed ECL board Reset medium speed ECL board Reset sample counters Enable medium speed ECL board S/P converter clocks Temperature sensor data clock Temperature sensor serial data


Table 2. Sampler-Correlator Cable Pin assignment. J1 J2 Wire Signal Signal 1 S0-D0 S8-D0 2 ~S0-D0 ~S8-D0 3 S0-D1 S8-D1 4 ~S0-D1 ~S8-D1 5 S1-D0 S9-D0 6 ~S1-D0 ~S9-D0 7 S1-D1 S9-D1 8 ~S1-D1 ~S9-D1 9 S2-D0 S10-D0 10 ~S2-D0 ~S10-D0 11 S2-D1 S10-D1 12 ~S2-D1 ~S10-D1 13 S3-D0 S11-D0 14 ~S3-D0 ~S11-D0 15 S3-D1 S11-D1 16 ~S3-D1 ~S11-D1 17 S4-D0 S12-D0 18 ~S4-D0 ~S12-D0 19 S4-D1 S12-D1 20 ~S4-D1 ~S12-D1 21 S5-D0 S13-D0 22 ~S5-D0 ~S13-D0 23 S5-D1 S13-D1 24 ~S5-D1 ~S13-D1 25 S6-D0 S14-D0 26 ~S6-D0 ~S14-D0 27 S6-D1 S14-D1 28 ~S6-D1 ~S14-D1 29 S7-D0 S15-D0 30 ~S7-D0 ~S15-D0 31 S7-D1 S15-D1 32 ~S7-D1 ~S15-D1 33 Clock Clock 34 ~Clock ~Clock

t Clock Data

clkper

Data and Clock transition at the same instant. SAMPLER-CORRELATOR DATA FORMAT


t Clock Data

clkdd

t

clkdd

SAMPLER-CORRELATOR DATA-CLOCK TIMING

Name Clock Period Clock-Data delay

Symbol tclkper tclkdd

Min 7.8 -0.25

Typ 0

Max 0.25

Units nS nS

INFORMATION IN THIS DOCUMENT IS PRELIMINARY AS DESIGN IS STILL IN PROGRESS END