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Cryogenic Phase Locking Loop System for Superconducting Integrated Receiver
Andrey Khudchenko, Valery Koshelets, Pavel Dmitriev, Andrey Ermakov - Institute of Radio Engineering and Electronics (IREE), Moscow, Russia Pavel Yagoubov - SRON Netherlands Institute for SpaceResearch, the Netherlands in collaboration with Oleksandr Pylypenko - State Research Center of Superconducting Electronics "Iceberg", Kyiv, Ukraine
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Cryogenic Phase Locking Loop System for Superconducting Integrated Receiver Outline
·
· · · · Introduction - Superconducting Integrated Receiver (SIR) FFO Phase Locking ­ performance and prospects SIS-junction as a Cryogenic Phase Detector (CPD) CPD and FFO coupling Cryogenic Phase Lock Loop system experimental results Conclusion
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·


Block Diagram of Superconducting Integrated Receiver
He 4.2K Local Oscillator ~ 600 GHz (FFO)
500 - 700 GHz

Antenna
~ 600 GHz

SIS mixer
20 GHz

4 - 8 GHz

IF

Harmonic SIS-mixer

Room Temperature PLL System
April 4, 2008

400 MHz 400 MHz

LO LO
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Superconducting Integrated Receiver (SIR)
· APPLICATIONS Airborne Receiver for Atmospheric Research and Environmental Monitoring; Radio Astronomy; Large Imaging Array Receiver Laboratory MM & subMM Spectrometer STATE OF THE ART Single chip Nb-AlOx-Nb SIS receivers with superconducting FFO has been studied at frequencies from 100 to 700 GHz A DSB receiver noise temperature as low as 90 K has been achieved at 500 GHz 9-pixel Imaging Array Receiver has been successfully tested Phase Locked operation from 550 to 700 GHz TELIS - balloon-borne spectrometer, the qualification flight is foreseen in May 2008
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· · · · ·


SIR FFO prospects

For future SIR applications (f>1THz) FFO with NbN electrodes will be used; FFO linewidth could considerably exceed 10 MHz. So ultrawideband PLL is required (>30 MHz). Cryogenic PLL with small power consumption for large SIR arrays

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Spectra of the FFO at 707.45 GHz
-10 IF Output Power (dBm) -15 -20 -25 -30 -35 707,40 707,42 707,44 707,46 707,48 707,50

Phase Locked at 707.45 GHz Frequency Locked

Span - 100 MHz Resolution bandwidth - 1 MHz

a)

FFO Frequency (GHz)

Spectral Ratio (SR) ­ the part of FFO power locked by PLL system
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Spectra of the phase-locked FFO for different delay in the PL loop
FFO LW = 3.4 MHz initial SR = 67 % Extra Cable : 2 3 4 5 6 7 8 m m m m m m m

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SR value on the delay in PL loop
0 -1 100

o

Loop length,
0

0

1

2

3

4

5

6

7

8

9

80 Spectral Ratio, % 60 40 20 0
LW=1.7 MHz LW=2.2 MHz LW=3.4 MHz

0

5

10 15 20 25 30 35 40 45 50 Group Delay, ns
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April 4, 2008


Idea of the Cryogenic Phase Lock Loop System
He 4.2K Local Oscillator ~ 600 GHz (FFO)
500 - 700 GHz

Antenna
~ 600 GHz

SIS mixer
20 GHz

4 - 8 GHz

IF

Cryogenic PLL system

Harmonic SIS-mixer

Room Temperature PLL System
April 4, 2008

400 MHz 400 MHz

LO LO
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SIS-junction a Cryogenic Phase
300 250 SIS Current (µA) 200 150 100 50 0 Autonomus only 1 Synt in phase contra phase Phase response

as Detector

90

I sis, µA

1

85 80 75 70 65 0 60 120 180 240 300 360

3 2 4 5

-50

Phase Differnce
0 1 2 3 4 5

SIS Voltage (mV)

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CPD and FFO coupling
I_SIS

I0
o o
CL

R

CPD FFO

V0

rd
dI
V_SIS
April 4, 2008 BjÆrkliden, Sweden

- CPD differential resistance

CL _ FFO

=-

rd I CPD dP rd + R P
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CPD output, I_pump(P)
-50 Pout, dBm -60 -70 -80 -90 -100 -80 -70 -60 -50 -40 Pinput 2, dBm -30 Direct measurement Calculation from I_pump(P)

500 400 I_CPD , µ 300 200 100 0 0

autonomus -52 dBm -48 dBm -44 dBm -40 dBm

1

2

3

4

5

V_CPD, V

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P_pump(P) model
I (Vdc , ,Vac ) =
eVac 10 h 15

n =-


25

+

J(

2 eVac n h

) I 0 (Vdc +

n h e

)

Simulations
20

0 100 I C PD , µ A 80 60 40 20

5

175 150 I CPD, µA 125 100 75 50 25 0

eVac = 0 (autonomus) h = 1

=5 = 10

Simulation result (f = 80 GHz)

f = 80 GHz
0 1 2 3 4
13

0 0.00 0.01 0.02 0.03 0.04 0.05 April 4, 2008 1/2 Signal Amplitude, Wt

Measurements (f = 4 GHz)

0.06

5

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V CPD, V


CryoPLL Block diagram
Room Temperature PLL
Spectrum Analyzer 600

18 GHz HM

400 MHz

FFO
T = 4.2 K Filter

1

CPD
LO 400 MHz BjÆrkliden, Sweden

2

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Photo of the CryoPLL

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Spectra of PLL and CryoPLL
CryoPLL
Autonomus (LW=2MHz) CryoPLL RoomTemperature PLL -20 -25 -30 -35 -40 -45 -50 -55 -60 -65
350 360 370 380 390 400 410 420 430 440 450 f , MHz
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RoomPLL

Loop length, : 1 2 Delay in elements, ns: 2 5 Total Delay, ns: 7 15 Bandwidth, MHz 27 12 SR, % (for LW=2 MHz) 91 82
16

P, dBm


Phase Noise
-60

RoomPLL CryoPLL

Phase Noise , dBc/Hz

-70

For FFO Linewidth 9 MHz PLL gives SR = 25% _CryoPLL - 53%!

-80

-90

-100 1000

10000

100000 1000000 Offset from carier (Hz)

1E7

1E8

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Conclusion
· New and successful application of SIS junction - cryogenic phase detector (CPD). · CPD intrinsically could operate with effective bandwidth more than 100 MHz. Maximal output signal is about 0.1 mV. · Concept of CryoPLL system is confirmed. Bandwidth 27 MHz has been obtained in the first experiments. · Improvement of the PLL FFO spectral ration from 20% to 50% has been achieved at application of the CryoPLL for FFO linewidth 10 MHz. · Practical application of the CPD looks especially promising for the development of SIR arrays.

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