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Cryogenic Phase Locking Loop System for Superconducting Integrated Receiver
Andrey Khudchenko1, Valery Koshelets1, Pavel Dmitriev1, Andrey Ermakov Pavel Yagoubov2, Oleksandr Pylypenko2
3State 2SRON 1Institute of Radio Engineering and Electronics, IREE, Russia Netherlands Institute for Space Research, the Netherlands Research Center of Superconducting Electronics "Iceberg", Ukraine

1,

Abstract
A bandwidth of the typical Phase Locking Loop (PLL) system for the Superconducting Integrated Receiver (SIR) is limited by unavoidable delays in the long cables between SIR inside cryostat semiconductor PLL system outside it. To overcome this limitation we propose Cryogenic Phase Locking Loop (CPLL). A cryogenic phase detector (CPD) based on a superconductor-insulator-superconductor (SIS) junction has been proposed and preliminary tested. A sinusoidal output signal of the CPD has been measured. Experimental data demonstrate that the CPD intrinsically could operate with an effective bandwidth more than 100 MHz. The CPD is initially intended for phase locking of the Flux-Flow Oscillator (FFO) in the SIR. A model describing coupling between a CPD and an FFO has been developed and experimentally verified. A design of the CPLL system for the SIR is presented. An effective bandwidth of the CPLL system exceeds 25 MHz at an operation frequency of 400 MHz. This is considerably better than bandwidth of the room-temperature PLL system which is limited to 12 MHz. The novel CPLL system synchronizes 50% of the FFO power for freerunning FFO linewidth of about 10 MHz, compare to 20% in the case of regular PLL system. It results in improvement of the FFO spectral ratio and would expand the SIR operation range.

Superconducting Integrated Receiver
4 K dewar SIR chip
SIS mixer Harmonic mixer FFO as LO 550-650 GHz

Ultrawideband PLL is required (>50 MHz):
For the future SIR applications (f>1THz) an FFO with the NbN electrodes will be used; the FFO linewidth could considerably exceed 10 MHz.

HEMT 4-8 GHz

IF Processor & DAC

The specification for a ALMA interferometer require a phase stability better then 75 fs. To realise such a stability for the SIR a part of phase locked FFO power ­ Spectral Ratio (SR), as hight as 90% is needed.
100

HEMT
4 GHz

Spectral Ratio (%)

20 GHz reference

Computer controlled data acquisition system Electronics FFO, SIS, HM control

80

60

PLL

LSU

40
Experimental Data; TELIS PLL JAP, 102, 063912 (2007) Simulation (by Andrey Pankratov) Regulation BW = 12 MHz Regulation BW = 36 MHz Regulation BW = 60 MHz

400 MHz reference

20

Schematics of the FFO stabilization circuit. FFO frequency is mixed in HM with the 19-21 GHz reference. The mixing product is amplified, downconverted and compared with the 400 MHz reference in the PLL. The phase difference signal generated by PLL is used to feedback the FFO control line.

0

1

10

Free-running FFO Linewidth (MHz)

The Dependence of the SR vs FFO linewidth for different PLL bandwidths.

100

-1

0

1

2

Loop Length, 3 45 6

7

8

9

Concept of the Cryogenic PLL
SIS - Cryogenic Phase Detector for the CPLL
300 250

80 Spectral Ratio, % 60 40 20 0

Room Temperature PLL Spectrum Analyzer

90
A tonom s u u signal 1 in phase contra phase Phase response

SIS Current (µA)

85

600 GHz

20 GHz

400 MHz

200 150 100 50 0 -50 0

I sis, µA

1

80 75 70

LW=1.7 MHz LW=2.2 MHz LW=3.4 MHz
0 5 10 15 20 25 30 35 Group Delay, ns 40 45 50

3 2 4

FFO
0 60 120 180 240 300 360

65
5

Harmonic Mixer

1
HEMT

Phase Differnce
4 5

1

2

3

SIS Voltage (m V)

I-VCs of a SIS junction. Microwave signals (5 GHz) are applied.

A SIS is a well known mixer element. Sinusoidal response of SIS in dependence on phase difference between coming microwave signals demonstrate it can be a CPD. The CPD could operate with effective bandwidth more than 100 MHz.

Filter
Cryostat T = 4.2 K LO 400 MHz

CPD 2

The PLL bandwidth is determined by a total group delay in the loop. A bandwidth of the typical PLL system for the SIR is limited by unavoidable delays in the long cables between the SIR inside a cryostat and semiconductor PLL system outside it. To overcome this limitation we propose the CPLL.

All the elements of the Cryogenic PL Loop are inside the cryostat with a FFO. It allows to minimize the loop length and the time delay.

Summary
A new and successful application of a SIS junction - cryogenic phase detector (CPD).
The CPD intrinsically could operate with an effective bandwidth more than 100 MHz. The maximal output signal is about 0.1 mV. A concept of CryoPLL system has been proven. Bandwidth as wide as 27 MHz has Hz been obtained in the first experiments.

Experimental realization of the CPLL
Loop length() Delay in elements(ns) Total Delay(ns) Bandwidth(MHz)

CryoPLL RoomPLL

1 2

2 5

15 7

27 12

-2 0 -2 5 -3 0 -3 5
P, dBm

Au to n o m u s (L W = 2 M H z ) C r yo PL L , SR = 91 % R o om Te m p e r a t u re P L L , S R = 8 2 %

-60

RoomPLL CryoPLL

The improvement of the phase locked FFO spectral ration from 20% to 50% has been achieved at application of the CryoPLL for FFO linewidth 10 MHz. ewidth Practical application of the CPD looks especially promising for the development of SIR arrays. The first CryoPLL system with operation frequency 4 GHz has been successfully tested.

Phase Noise , dBc/Hz

-70

-4 0 -4 5 -5 0 -5 5 -6 0 -6 5
35 0 3 60 37 0 3 8 0 39 0 4 0 0 4 1 0 4 2 0 4 3 0 4 40 45 0 f , M Hz

-80

-90

-100 1000

10000

100000 1000000 Offset from carier (Hz)

1E7

1E8

Photo of the CPLL in cryostat. FFO and CPD are placed in two separated shields. Length of the loop is 1m.

Downconverted spectra of FFO. The The CPLL demonstrate a better Phase Noise demonstration of CPLL advantage - for linewidth then the Room Temperature PLL at 2 MHz it gives SR = 91% as contrasted with frequencies more then 10kHz . 82% for the Room Temperature PLL system.

For further information please contact: Khudchenko@hitech.cplire.ru ISSTT 2008 The Netherlands.