Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/sp/build/Makefile Дата изменения: Thu Jun 26 04:27:56 2008 Дата индексирования: Sat Sep 6 20:00:54 2008 Кодировка: Поисковые слова: http www.astronomy.ru forum index.php topic 4644.0.html

include ../src/Makefile.defs

# Jeff Mock
# 2030 Gough St.
# San Francisco, CA 94109
# jeff@mock.com
#
# Copyright 2005,2006
#
# $URL: https://www.mock.com/svn/pdev/trunk/gx/sp/build/Makefile $
# $Id: Makefile 1027 2007-09-21 03:31:18Z jeff $
#

PFBIMP = rtl
CMIXIMP = rtl
DLPFIMP = rtl

GUIDE = guide.ncd
# With N_HR enabled, the build time for the FPGA is getting
# out of hand using version 8.1sp3 of the Xilinx tools. This
# can be improved by chossing a good seed for building the chip.
# "make many" will try to build the chip with consecutive seed
# values until it builds properly. "make" builds the chip once
# using this starting seed value. A good seed value might build
# the chip in 2-hours (August 2007), a bad seed value might fail
# after 12-hours of routing. Choosing a good seed is more luck
# than engineering.
#
SEED = 1


all: ${NR}.bin.gz ${NR}.twr

sim: ${N}.v

${NR}.bin.gz: ${NR}.bit
${PROMGEN} -w -p bin -u 0 ${NR}.bit ${NR}.bit -o ${NR}
gzip -f -9 ${NR}.bin

${NR}.bit: ${NR}.ncd
${BITGEN} -w ${NR}.ncd ${NR}.bit

${N}.v: ${N}.ngd
${NGD2VER} -w ${N}.ngd

# Generate gate level verilog netlist from routed chip
${NR}.v: ${NR}.ncd
${NGDANNO} -o ${NR}.nga -p ${N}.pcf ${NR}.ncd
${NGD2VER} -w ${NR}.nga

# Run static timing analyzer on routed chip
${NR}.twr: ${NR}.ncd
${TRCE} -v 100 ${NR}.ncd ${N}.pcf

# Run a lot of place and routes for difficult design
many: ${N}.ncd
${PAR} -t ${SEED} -n 0 -ol high -rl std -w ${N}.ncd ${NR} ${N}.pcf

# Place and route ncd file into new ncd file
${NR}.ncd: ${N}.ncd
${PAR} -t ${SEED} -ol high -w ${N}.ncd ${NR} ${N}.pcf

# Place and route ncd file into new ncd file using guide file
guide: ${N}.ncd
${PAR} -t ${SEED} -ol high -w ${N}.ncd ${NR} ${N}.pcf \
-gm exact -gf ${GUIDE}

# Map netlist into unrouted .ncd file
${N}.ncd: ${N}.ngd
rm -rf ${N}.ncd
${MAP} -pr b ${N}.ngd -o ${N}.ncd ${N}.pcf

# Turn ngc netlist and constraint file into ngd netlist
${N}.ngd: ${N}.ngc ${UCF}
${NGDBUILD} -sd ${PLINTH}/build -uc ${UCF} ${N}

# Synthesize the whole chip at once and make .ngc netlist file
${N}.ngc: ${N}.cmd ${N}.prj ${SRCVH} ${SRCV}
${XST} -ifn ${N}.cmd -ofn log.xst

# This makes the command file for running XST synthesis
#
${N}.cmd: Makefile
rm -rf ${N}.cmd
echo "identification" >> ${N}.cmd
echo "status" >> ${N}.cmd
echo "time short" >> ${N}.cmd
echo "memory on" >> ${N}.cmd
echo "run -ifn ${N}.prj \
-top gx \
-ifmt VERILOG \
-ofn ${N} \
-p ${PART} \
-opt_level 2 \
-keep_hierarchy soft \
-equivalent_register_removal no \
-max_fanout 65535" \
>> ${N}.cmd

${PFBDIR}: Makefile
${MAKE} -C ${PFB} ${PFBIMP}

${CMIXDIR}: Makefile
${MAKE} -C ${CMIX} ${CMIXIMP}

${DLPFDIR}: Makefile
${MAKE} -C ${DLPF} ${DLPFIMP}

# This makes the project file for running XST synthesis, basically
# it's just a bunch of verilog include statements for the files that
# make up the chip.
#
${N}.prj: Makefile ${PFBDIR} ${CMIXDIR} ${DLPFDIR}
rm -rf ${N}.prj
echo "\`define VIRTEX2 1" >> ${N}.prj
echo "\`define ${CHIP}" >> ${N}.prj
echo "\`define DIE_${DIE}" >> ${N}.prj
for i in ${SRCVH} ${SRCV} ${PFBDIR}/*.v ${CMIXDIR}/*.v ${DLPFDIR}/*.v ; do \
echo "\`include \"$$i\"" >> ${N}.prj ; \
done

clean:
rm -rf log.xst xst *.lst *.log *.bld *.bin *.prm ${N}.ncd
rm -rf *.bld *.mrp *.ngc *.ngd *.ngm *.pcf *.alf *.csv
rm -rf *.pad *.txt *.par *.sdr *.twr *.v *.xpi *.sdf *.nga
rm -rf ${N}.cmd ${N}.prj ${NR}.* *.ngo ${CMIXDIR} ${DLPFDIR}
${MAKE} -C ${PFB} clean