Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/plinth/src/gx.v Дата изменения: Thu Jun 26 04:26:02 2008 Дата индексирования: Sat Sep 6 19:52:07 2008 Кодировка: Поисковые слова: http astrokuban.info astrokuban

// Jeff Mock
// 2030 Gough St.
// San Francisco, CA 94109
// jeff@mock.com
//
// Copyright 2005,2006
//
// $URL: https://www.mock.com/svn/pdev/trunk/gx/plinth/src/gx.v $
// $Id: gx.v 917 2007-02-25 01:15:47Z jeff $


// Top of FPGA
//

module gx (
adc0_clkp,
adc0_clkn,
adc0_datp,
adc0_datn,
adc0_ovlp,
adc0_ovln,
adc1_clkp,
adc1_clkn,
adc1_datp,
adc1_datn,
adc1_ovlp,
adc1_ovln,
adc2_clkp,
adc2_clkn,
adc2_datp,
adc2_datn,
adc2_ovlp,
adc2_ovln,
adc3_clkp,
adc3_clkn,
adc3_datp,
adc3_datn,
adc3_ovlp,
adc3_ovln,

pi_ck,
pi_resetb,
pi_addr,
pi_data,
pi_par,
pi_csb,
pi_rd,
pi_oeb,
pi_web,
pi_lastb,
pi_ready,
pi_err,
pi_dmareq,
// pi_dmaack,
// pi_dmaeot,
pi_int,

qdr_kp,
qdr_kn,
qdr_cp,
qdr_cn,
qdr_cqp,
qdr_cqn,
qdr_a,
qdr_di,
qdr_do,
qdr_reb,
qdr_web,
qdr_bweb,
qdr_doffb,

master,
board_rev,
adc_rev,

gp_in,
gp_sync,
gp_oeb,
gp_out,

adcclk_sel,
adcclk_en,

// mgt_clkp,
// mgt_clkn,

extra_cc,
extra_hdr,
keep
);

// ADC input pads
input adc0_clkp;
input adc0_clkn;
input [`N_ADC-1:0] adc0_datp;
input [`N_ADC-1:0] adc0_datn;
input adc0_ovlp;
input adc0_ovln;
input adc1_clkp;
input adc1_clkn;
input [`N_ADC-1:0] adc1_datp;
input [`N_ADC-1:0] adc1_datn;
input adc1_ovlp;
input adc1_ovln;
input adc2_clkp;
input adc2_clkn;
input [`N_ADC-1:0] adc2_datp;
input [`N_ADC-1:0] adc2_datn;
input adc2_ovlp;
input adc2_ovln;
input adc3_clkp;
input adc3_clkn;
input [`N_ADC-1:0] adc3_datp;
input [`N_ADC-1:0] adc3_datn;
input adc3_ovlp;
input adc3_ovln;

// powerpc peripheral bus interface
input pi_ck;
input pi_resetb;
input [23:0] pi_addr;
inout [31:0] pi_data;
inout [3:0] pi_par;
input [7:1] pi_csb;
input pi_rd;
input pi_oeb;
input pi_web;
input pi_lastb;
output pi_ready;
output pi_err;
output [1:0] pi_dmareq;
// input [1:0] pi_dmaack;
// input [1:0] pi_dmaeot;
output [3:0] pi_int;

// QDR SRAM
output qdr_kp;
output qdr_kn;
output qdr_cp;
output qdr_cn;
input qdr_cqp;
input qdr_cqn;
output [19:0] qdr_a;
input [35:0] qdr_di;
output [35:0] qdr_do;
output qdr_reb;
output qdr_web;
output [3:0] qdr_bweb;
output qdr_doffb;

// option external pulldown for slave FPGA
inout master;
inout [3:0] board_rev;
inout [7:0] adc_rev;

// GPIO pins and multi-chip sync
input [`GP_IN-1:0] gp_in;
inout [`GP_IN-1:0] gp_sync;
output [`GP_IN-1:0] gp_oeb;
output [`GP_IN-1:0] gp_out;

// GPouts to control clock to ADCs
output adcclk_sel;
output adcclk_en;

// Refclk for the serdes
//
// input mgt_clkp;
// input mgt_clkn;

// Extra signals
inout [35:0] extra_cc;
inout [35:0] extra_hdr;
output keep;

// Write interface to diagnostic registers
//
wire ctl_we;
wire [15:0] ctl_addr;
wire [15:0] ctl_data;
wire [15:0] ctl_rd_data;

// PI control registers
wire [19:0] preg_pfifo_len;
wire [7:0] preg_ramcfg;
wire [15:0] preg_packdiag;
wire [2:0] preg_swap;

// Resets
wire reset_pfifo;
wire reset;

// r/o status registers
//
wire sreg_pfifo_over;
wire sreg_pfifo_under;
wire [15:0] sreg_pmax;

// pullup master/slave strap
//
PULLUP pu_master (
.O ( master )
);

`ifdef XXX
wire mgt_clk;
wire brefclk2;
mgtclk mgtclk (
.mgt_clkp ( mgt_clkp ),
.mgt_clkn ( mgt_clkn ),
.mgt_clk ( mgt_clk ),
.brefclk2 ( brefclk2 )
);
`endif

wire adc_dcm_reset;
wire adc_dcmret_reset;
wire ck; // ADC clock
wire ck180; // ADC clock plus 180-degrees
wire ck_cqp_90;
wire ck_cqn_90;
wire k1;
wire qdr_k_en;
wire qdr_c_en;
wire ps_clk;
wire ps_incdec;
wire ps_en;
wire ce;
wire ckce;
adcclk adcclk (
.adc_dcm_reset ( adc_dcm_reset ),
.adc_dcmret_reset ( adc_dcmret_reset ),

.ps_clk ( ps_clk ),
.ps_incdec ( ps_incdec ),
.ps_en ( ps_en ),

.adc0_clkp ( adc0_clkp ),
.adc0_clkn ( adc0_clkn ),
.adc1_clkp ( adc1_clkp ),
.adc1_clkn ( adc1_clkn ),
.adc2_clkp ( adc2_clkp ),
.adc2_clkn ( adc2_clkn ),
.adc3_clkp ( adc3_clkp ),
.adc3_clkn ( adc3_clkn ),

.ck ( ck ),
.ck180 ( ck180 ),
.ce ( ce ),
.ckce ( ckce ),

.qdr_kp ( qdr_kp ),
.qdr_kn ( qdr_kn ),
.qdr_cp ( qdr_cp ),
.qdr_cn ( qdr_cn ),
.qdr_cqp ( qdr_cqp ),
.qdr_cqn ( qdr_cqn ),

.ck_cqp_90 ( ck_cqp_90 ),
.ck_cqn_90 ( ck_cqn_90 ),

.qdr_k_en ( qdr_k_en ),
.qdr_c_en ( qdr_c_en ),
.keep ( k1 )
);

// Condition general purpose inputs (pps, cal, blank, etc)
// and sync across multiple fpgas.
//
wire [`GP_IN-1:0] gp;
wire [`GP_IN-1:0] preg_gpinv;
wire [`GP_IN-1:0] preg_gpintsel;
wire [`GP_IN-1:0] preg_gpforce;
gpin gpin (
.ck ( ck ),
.reset ( reset ),
.master ( master ),

.gp_in ( gp_in ),
.gp_inv ( preg_gpinv ),
.gp_intsel ( preg_gpintsel ),
.gp_force ( preg_gpforce ),
.gp_sync ( gp_sync ),

.gp ( gp )
);

// LVDS ADC input pads
//
wire [`N_ADC-1:0] adc0_dat;
wire adc0_ovl;
wire [`N_ADC-1:0] adc1_dat;
wire adc1_ovl;
wire [`N_ADC-1:0] adc2_dat;
wire adc2_ovl;
wire [`N_ADC-1:0] adc3_dat;
wire adc3_ovl;
wire [`N_ADC-1:0] preg_adc0_off;
wire [`N_ADC-1:0] preg_adc1_off;
wire [`N_ADC-1:0] preg_adc2_off;
wire [`N_ADC-1:0] preg_adc3_off;
wire [15:0] preg_adc0_scale;
wire [15:0] preg_adc1_scale;
wire [15:0] preg_adc2_scale;
wire [15:0] preg_adc3_scale;
adcpad adc0 (
.ck ( ck ),
.cko ( ck ),
.adc_off ( preg_adc0_off ),
.adc_scale ( preg_adc0_scale ),
.datp ( adc0_datp ),
.datn ( adc0_datn ),
.ovlp ( adc0_ovlp ),
.ovln ( adc0_ovln ),
.dat ( adc0_dat ),
.ovl ( adc0_ovl )
);
adcpad adc1 (
.ck ( ck ),
.cko ( ck ),
.datp ( adc1_datp ),
.adc_off ( preg_adc1_off ),
.adc_scale ( preg_adc1_scale ),
.datn ( adc1_datn ),
.ovlp ( adc1_ovlp ),
.ovln ( adc1_ovln ),
.dat ( adc1_dat ),
.ovl ( adc1_ovl )
);
adcpad adc2 (
.ck ( ck ),
.cko ( ck ),
.adc_off ( preg_adc2_off ),
.adc_scale ( preg_adc2_scale ),
.datp ( adc2_datp ),
.datn ( adc2_datn ),
.ovlp ( adc2_ovlp ),
.ovln ( adc2_ovln ),
.dat ( adc2_dat ),
.ovl ( adc2_ovl )
);
adcpad adc3 (
.ck ( ck ),
.cko ( ck ),
.adc_off ( preg_adc3_off ),
.adc_scale ( preg_adc3_scale ),
.datp ( adc3_datp ),
.datn ( adc3_datn ),
.ovlp ( adc3_ovlp ),
.ovln ( adc3_ovln ),
.dat ( adc3_dat ),
.ovl ( adc3_ovl )
);

// The signal processor
//
wire [63:0] pack_dat_sp;
wire pack_vld_sp;
wire [15:0] sp_id;
wire [`GP_IN-1:0] gp_out_sp;
wire [`GP_IN-1:0] preg_gpsel;
wire [`GP_IN-1:0] preg_gpout;
wire obs_start;
wire obs_stop;
sp sp (
.ck ( ck ),
.ce ( ce ),
.ckce ( ckce ),
.reset ( reset ),
.master ( master ),
.obs_start ( obs_start ),
.obs_stop ( obs_stop ),

.ctl_we ( ctl_we ),
.ctl_addr ( ctl_addr ),
.ctl_data ( ctl_data ),
.ctl_rd_data ( ctl_rd_data ),

.gp ( gp ),
.gp_out ( gp_out_sp ),

.adc0_dat ( adc0_dat ),
.adc0_ovl ( adc0_ovl ),
.adc1_dat ( adc1_dat ),
.adc1_ovl ( adc1_ovl ),
.adc2_dat ( adc2_dat ),
.adc2_ovl ( adc2_ovl ),
.adc3_dat ( adc3_dat ),
.adc3_ovl ( adc3_ovl ),

.pack_dat ( pack_dat_sp ),
.pack_vld ( pack_vld_sp ),

.sp_id ( sp_id ),

.extra_cc ( extra_cc ),
.extra_hdr ( extra_hdr )
);

// gp_out normally comes from the sp. For diagnostics
// or maybe simple GPIO outputs, pi registers can select
// pi for gp_out instead of the sp. If the preg_gpsel bit
// is set, gp_out is driven by the bit in preg_gpout.
//
reg [`GP_IN-1:0] gp_out;
always @(posedge ck)
gp_out <= (preg_gpout & preg_gpsel) | (gp_out_sp & ~preg_gpsel);

wire [63:0] pack_dat_diag;
wire pack_vld_diag;
pack_diag pack_diag (
.ck ( ck ),
.reset ( reset ),
.preg_packdiag ( preg_packdiag ),
.preg_pfifo_len ( preg_pfifo_len ),

.adc0_dat ( adc0_dat ),
.adc0_ovl ( adc0_ovl ),
.adc1_dat ( adc1_dat ),
.adc1_ovl ( adc1_ovl ),
.adc2_dat ( adc2_dat ),
.adc2_ovl ( adc2_ovl ),
.adc3_dat ( adc3_dat ),
.adc3_ovl ( adc3_ovl ),

.pack_dat ( pack_dat_diag ),
.pack_vld ( pack_vld_diag )
);

// Mux pack_diag and sp output
//
reg [63:0] pack_dat;
reg pack_vld;
always @(posedge ck) begin
pack_dat <= preg_packdiag[15] ? pack_dat_diag : pack_dat_sp;
pack_vld <= preg_packdiag[15] ? pack_vld_diag : pack_vld_sp;
end

// External sram fifo to hold packed data from sp
//
wire pfo_re;
wire pfo_ready;
wire [63:0] pfo_dat;
wire [7:0] pfo_datp;
wire pfo_vld;
pack_fifo pack_fifo (
.ck ( ck ),
.ck180 ( ck180 ),
.reset_pfifo ( reset_pfifo ),

.preg_pfifo_len ( preg_pfifo_len ),
.preg_ramcfg ( preg_ramcfg ),
.preg_swap ( preg_swap ),
.sreg_pfifo_over ( sreg_pfifo_over ),
.sreg_pfifo_under ( sreg_pfifo_under ),
.sreg_pmax ( sreg_pmax ),

.pack_dat ( pack_dat ),
.pack_vld ( pack_vld ),

.pfo_re ( pfo_re ),
.pfo_ready ( pfo_ready ),
.pfo_dat ( pfo_dat ),
.pfo_datp ( pfo_datp ),
.pfo_vld ( pfo_vld ),

.ck_cqp_90 ( ck_cqp_90 ),
.ck_cqn_90 ( ck_cqn_90 ),
.qdr_a ( qdr_a ),
.qdr_di ( qdr_di ),
.qdr_do ( qdr_do ),
.qdr_reb ( qdr_reb ),
.qdr_web ( qdr_web ),
.qdr_bweb ( qdr_bweb ),
.qdr_doffb ( qdr_doffb )
);

// powerpc processor interface
//
wire k2;
pi pi (
.ck ( ck ),

.ps_clk ( ps_clk ),
.ps_incdec ( ps_incdec ),
.ps_en ( ps_en ),

.pi_ck ( pi_ck ),
.pi_resetb ( pi_resetb ),
.pi_dmareq ( pi_dmareq ),
// .pi_dmaack ( pi_dmaack ),
// .pi_dmaeot ( pi_dmaeot ),
.pi_addr ( pi_addr ),
.pi_data ( pi_data ),
.pi_par ( pi_par ),
.pi_csb ( pi_csb ),
.pi_rd ( pi_rd ),
.pi_oeb ( pi_oeb ),
.pi_web ( pi_web ),
.pi_lastb ( pi_lastb ),
.pi_ready ( pi_ready ),
.pi_err ( pi_err ),
.pi_int ( pi_int ),

.master ( master ),

.pfo_re ( pfo_re ),
.pfo_ready ( pfo_ready ),
.pfo_dat ( pfo_dat ),
.pfo_datp ( pfo_datp ),
.pfo_vld ( pfo_vld ),

.ctl_we ( ctl_we ),
.ctl_addr ( ctl_addr ),
.ctl_data ( ctl_data ),
.ctl_rd_data ( ctl_rd_data ),

.preg_pfifo_len ( preg_pfifo_len ),
.preg_ramcfg ( preg_ramcfg ),
.preg_packdiag ( preg_packdiag ),
.preg_swap ( preg_swap ),
.preg_gpinv ( preg_gpinv ),
.preg_gpintsel ( preg_gpintsel ),
.preg_gpforce ( preg_gpforce ),
.preg_adc0_off ( preg_adc0_off ),
.preg_adc1_off ( preg_adc1_off ),
.preg_adc2_off ( preg_adc2_off ),
.preg_adc3_off ( preg_adc3_off ),
.preg_adc0_scale ( preg_adc0_scale ),
.preg_adc1_scale ( preg_adc1_scale ),
.preg_adc2_scale ( preg_adc2_scale ),
.preg_adc3_scale ( preg_adc3_scale ),

.sreg_pfifo_over ( sreg_pfifo_over ),
.sreg_pfifo_under ( sreg_pfifo_under ),
.sreg_pmax ( sreg_pmax ),
.sp_id ( sp_id ),
.board_rev ( board_rev ),
.adc_rev ( adc_rev ),
.adcclk_sel ( adcclk_sel ),
.adcclk_en ( adcclk_en ),
.qdr_k_en ( qdr_k_en ),
.qdr_c_en ( qdr_c_en ),

.gp_oeb ( gp_oeb ),
.gp ( gp ),
.preg_gpsel ( preg_gpsel ),
.preg_gpout ( preg_gpout ),

.reset ( reset ),
.reset_pfifo ( reset_pfifo ),
.adc_dcmret_reset ( adc_dcmret_reset ),
.adc_dcm_reset ( adc_dcm_reset ),

.obs_start ( obs_start ),
.obs_stop ( obs_stop ),

.keep ( k2 )
);

reg keep;
always @(posedge ckce)
keep <= k1 ^ k2;
endmodule