Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/plinth/src/gx.vh Дата изменения: Thu Jun 26 04:26:02 2008 Дата индексирования: Sat Sep 6 20:00:39 2008 Кодировка: Поисковые слова: molecular cloud

// Jeff Mock
// 2030 Gough St.
// San Francisco, CA 94109
// jeff@mock.com
//
// Copyright 2005,2006
//
// $URL: https://www.mock.com/svn/pdev/trunk/gx/plinth/src/gx.vh $
// $Id: gx.vh 876 2007-02-04 05:03:04Z jeff $

`timescale 1ns / 1ps

// defines used throughout the design
//

// This is resistor programmed on the board.
//
`define BOARD_REV_SIM 4'he

// 8-wires from the ADC board, for convention let's say that
// 4 of them are for future function and the lower 4-bits are
// the board rev of the ADC.
//
`define ADC_REV_SIM 8'he

// Revision for the plinth code
`define PLINTH_VER 16'h0001

// Use four outputs of a single DCM to generate four clock phases
// for output pads to the SRAM. (otherwise use two phases and
// local clock inversion in the bonding pads generate four phases).
//
// `define ADCDCM_4P

// Do xapp685 technique of putting a blackbox of magic logic
// between DCM and BUFG to make the 0-degree and 90-degree clocks
// more symmetrical.
//
`define ADCDCM_FIX

// PPC registers
`define PREG_TEST 16'd0
`define PREG_TEST2 16'd1
`define PREG_PSTAT1 16'd2
`define PREG_PSTAT2 16'd3
`define PREG_PFIFO_LWM 16'd4
`define PREG_PFIFO_HWM 16'd5
`define PREG_DMA_BL 16'd6
`define PREG_DMA_CHAN 16'd7
`define PREG_PFIFO_LEN_H 16'd8
`define PREG_PFIFO_LEN_L 16'd9
`define PREG_RD_ADDR 16'd10
`define PREG_RD_DATA 16'd11
`define PREG_RESET 16'd12
`define PREG_RESET_PFIFO 16'd13
`define PREG_RAMCFG 16'd14
`define PREG_PACKDIAG 16'd15
`define PREG_SWAP 16'd16
`define PREG_PSTAT3 16'd17
`define PREG_CLKCTL 16'd18
`define PREG_GPOE 16'd19
`define PREG_ADCCNT 16'd20
`define PREG_PIDIAG 16'd21
`define PREG_GPIN 16'd22
`define PREG_GPSEL 16'd23
`define PREG_GPOUT 16'd24
`define PREG_PMAX 16'd25
`define PREG_GPINTSEL 16'd26
`define PREG_GPFORCE 16'd27
`define PREG_PPSSEL 16'd28
`define PREG_RUN 16'd29
`define PREG_GPINV 16'd30
`define PREG_GPSTICKY 16'd31
`define PREG_ADC0_OFFSET 16'd32
`define PREG_ADC1_OFFSET 16'd33
`define PREG_ADC2_OFFSET 16'd34
`define PREG_ADC3_OFFSET 16'd35
`define PREG_ADC0_SCALE 16'd36
`define PREG_ADC1_SCALE 16'd37
`define PREG_ADC2_SCALE 16'd38
`define PREG_ADC3_SCALE 16'd39
`define PREG_PLINTH_VER 16'd40

// Number of general purpose timing inputs (PPS, blanking, etc)
`define GP_IN 4

// Width of ADC inputs, needs to match instantiation of LVDS
// recievers in adcpad.v.
//
`define N_ADC 12