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FPGA P-ALFA backend

GALFA 3rd Meeting 2004-08-29 Arecibo Observatory
Giacomo Comes


P-Alfa backend requirements


Bandwidth Channels Input Levels Output levels Integration ti m e Number of products

300 MHz 1000 (300 KHz resolution) 8 bits (minimum) 4 bits (software) after mean subtraction 64 us (pulsar) 1 ms (continuum) 1 summed channel (pulsar) 4 (continuum)


P-Alfa backend implementation


Bandwidth Channels Input Levels Output levels Integration ti m e Number of products

300 MHz 1536 (200 KHz resolution) 12 bits 18 bits (hardware) flexible (software) 66.5 us (pulsar) 1 ms (continuum) 1 summed channel (pulsar) 4 (continuum)


One of Seven ALFA Channels
Rackmount Server PC running Linux 12-Bit Digitizer 100-200 MHz filter 12-Bit Digitizer ALFA CH 0A 200-300 MHz filter 12-Bit Digitizer 300-400 MHz filter ALPHA-DATA PMC Board ADM-XPL Xilinx Virtex I I Pro FPGA 12-Bit Digitizer 100-200 MHz filter 12-Bit Digitizer ALFA CH 0B 200-300 MHz filter 12-Bit Digitizer 300-400 MHz filter ALPHA-DATA PMC Board ADM-XPL Xilinx Virtex I I Pro FPGA SCSI Disk Drive
PCI Bus

ALPHA-DATA PMC Board ADM-XPL Xilinx Virtex I I Pro FPGA


ALPHA DATA ADM-XPL


PCI Mezzanine card Xilinx Virtex II Pro 2VP20/30 66MHz 64-bit PCI bus Up to 64 LVDS I/O Cost: $5000


ALPHA DATA products line
Different Xilinx devices supported Easy scalability
Device 2VP20 2VP30 2VP70 2VP100 2VP125 Logic Cells BRAM 20880 30816 74448 99216 125136 1584 2448 5904 7992 10008 Multipliers 88 136 328 444 556


FPGA block diagram
FI R filter FF T Demuxer Accumulator Local Bus I /O



Polyphase filter 1024-point pipeline FFT Sequence demuxer 22-bit integer accumulator 3x7 such modules (worst case) further optimization may reduce it




Current Status


The following System Generator block design is done
2n point ­ 2 stream pipeline FFT bit-reverse and sequence demuxer Accumulator Alpha Data PCI I/O Buffer





Linux kernel driver and library working Test C program working


Pipeline FFT


100% efficiency using two input streams
a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0

F FT

B3 B1 B2 B0 A3 A1 A2 A0 B7 B5 B6 B4 A7 A5 A6 A4



bit reverse and sequence demux required
B3 B1 B2 B0 A3 A1 A2 A0 B7 B5 B6 B4 A7 A5 A6 A4

DMX

A7 A6 A5 A4 A3 A2 A1 B7 B6 B5 B4 B3 B2 B1 B0


Example test circuit


PC to FPGA data write FPGA data processing FPGA to PC data read


I/O buffer circuit


PC


Next Steps


Polyphase filter DMA FPGA to PC access