Multi-Phase
Pinned Operation
(MPP)

CCD ESD Gate
Protection

Device
Specifications

Features:

2048 x 2048 pixel format

Front-illuminated
or thinned, back-
illuminated version

Unique thinning
and QE
enhancement processes

Excellent QE from
IR to UV

Anti-reflection coating for visible
region

Mechanical rigidity

MPP technology

Low dark current

Excellent charge transfer efficiency (CTE) at all signal levels

On-chip output MOSFET for low noise

Wide dynamic
range

Serial-parallel-
serial architecture with output MOSFET's in each quadrant for maximized readout flexibility

Applications
include:

Astronomy

Machine Vision

Medical Imaging

X-ray imaging

Scientific Imaging

SITe 2048 x 2048 Scientific-Grade CCD

SI-424A CCD Imager: Ideal for applications with medium-area imaging requirements

General Description

The SI-424A CCD Imager is a silicon charge-coupled device designed to efficiently image scenes at low light levels from UV to near infrared. The sensor is fabricated as a 2048 x 2048 pixel, full frame area imager that utilizes a buried channel, three level polysilicon gate process. Features include a buried channel with a mini-channel for high transfer efficiency, multi-phase pinned (MPP) operation for low dark current, and lightly doped drain (LDD) output amplifiers for low read noise. The device is available in a front illuminated version or a thinned, back-illuminated version that provides superior quantum efficiency.

SITe's unique thinning and back surface enhancement process provides increased blue and UV response in a flat and fully supported die. The CCD imager is mounted in a non-hermetic metal package without a window.

Functional Description

Imaging Area

As shown in the functional diagram, Figure 3, the imaging area of the SI424A consists of 2048 columns, each of which contains 2049 picture elements (pixels). Each pixel measures 24µm x 24µm. The columns are isolated from each other by channel-stop regions. The 2049 rows of pixels are further divided into two groups of 1025 rows (upper section) and 1024 rows (lower section) for clocking flexibility and output amplifier selection. There is an output amplifier at each corner of the device, at each end of the two output serial registers. By proper phasing of the parallel and serial clocks any or all of the four amplifiers may be selected.

The signal charge collected in the imaging array is transferred along the columns, one row at a time, to one or both of the serial registers and from there to the desired output amplifiers. The serial registers are also divided into two sections. Thus the array can be divided into quadrants to maximize data transfer rate. The four quadrants are designated by the letters a,b,c,d, corresponding to the nearest output amplifier.

Three levels of polysilicon are used to fabricate the three gate electrodes which form the basic CCD cell (pixel). All of the pixels in a given row are defined by the same three gates. Corresponding gates in each row within a group of 1024 or 1025 are connected in parallel at both edges of the array. The clock signals used to drive the imaging area gates are brought in from both edges of the array, thus increasing the rate at which the rows can be shifted. The two sections of the imaging area are bussed independently for phases 1 and 2, but the phase 3 bus is common to both sections.

Serial Registers

The functional diagram (Figure 3) illustrates the relationship between the imaging array and the serial registers. The charge collected in the imaging section is transferred through the transfer gate into the serial register phase 2 gate. The serial register has one pixel for each column in the imaging array, plus 20 extra pixels at each end for a total of 2088. The extra pixels serve as dark reference and ensure that the signal chain is stabilized when the image data is received at the output.

Figure 1 Output Structure

The output of each end of both serial registers is terminated in a summing well, a DC-biased last gate (which serves to decouple the serial clock pulses from the output node), and an output amplifier. The summing well is a separately clocked gate equal in charge capacity to the other serial gates. It can be used to provide on-chip (noiseless) charge summing of consecutive serial pixels. Similarly, it is possible to sum pixels into the serial register by performing repetitive parallel transfers with the serial clocks fixed. In this manner, it is possible to collect and detect as one pixel the sum of the charge in sub-arrays of the imaging section, provided that the sum is less than the full well charge. The well capacity of a pixel in the serial register is greater than that of a parallel pixel to ensure that the CTE remains high.

The two sections of the serial registers are bussed separately for phases 1 and 3, but the phase 2 bus is common to both sections within each serial register. As a result, S2ab and S2cd are driven by a common phase 2 clock for each specific register.

This architecture permits images to be read out of any one or all of the four output amplifiers in a variety of ways. Four major options are represented in the CCD timing diagrams and are described in a later section.

Output Structure

The imager has four output MOSFETs that are located in each corner of the device at the ends of the extended serial registers. Figure 1 presents a schematic diagram of each output configuration.

In operation, a positive pulse is applied to the reset gate (RGx). This sets the potential of the floating diffusion to the potential applied to the reset transistor drain (RDx). The reset gate voltage is then turned off and the output node (the floating diffusion) is isolated from the rest of the circuit. Charge from the serial pixel is then transferred to the output node on the falling edge of the summing well (SWx) clock signal. The addition of charge on the output node causes a change in the voltage on the gate of the output MOSFET. This change in voltage is sensed at OUTx.

Timing

The SITe SI424A CCD Imager can be operated with one, two, three or four outputs operating simultaneously. The serial gates are separated into left and right halves. Similarly, the parallel gates are separated into upper and lower halves. The quadrants thus formed are designated a (upper left), b (upper right), c (lower left), and d (lower right). See Figure 3.

When operated in the full frame mode, the entire imager’s signal is transferred to one output, and all of the same numbered phases of the selected serial register are clocked together. For example, S1c and S1d would be wired together. Likewise, in the parallel registers, P1a, P1b, P1c and P1d would all be wired and clocked together. The signal charge may be clocked out of any output; however, the timing must be appropriate for that output. The transfer gate (TG) adjacent to the chosen serial register must be clocked. The other transfer gate should be held low to prevent unwanted charge in the unused serial register from entering the parallel register. The unused serial register’s gates could be either clocked or held at the proper dc level.

The SI424A may also be operated in the quad mode wherein the signal charge is clocked out of all four outputs simultaneously. The charge in each quadrant is transferred to the nearest output. The gates in each quadrant are given clocking signals appropriate for full frame operation of that output. For example, S1a, S2ab, S3a and SWa would be clocked according to OUTa timing, and S1a, S2ab, S3b and SWb would be clocked according to OUTb timing. Likewise, the parallels, P1a, P1b, P2a, P2b, P3a, P3b, TGa and TGb should all be clocked according to OUTa and OUTb parallel timing, and the lower half parallel and serial clocks would be clocked according to OUTc and OUTd timing.

Finally, the SI424A may be operated with two simultaneous outputs by splitting either the serial or the parallel clocks. Timing for each of the halves must be appropriate for the chosen outputs. For example, to operate the split serials using outputs A and B; S1a, S2ab, S3a and SWa would be clocked according to OUTa serial timing while S1b, S2ab, S3b, and SWb would be clocked according to OUTb serial timing. The parallels would be operated as for full-frame using either OUTa or OUTb parallel timing. To operate with a parallel split, the parallels would be operated in the quad split mode, while the serials would be clocked in the full-frame mode.

Timing diagrams for each output are shown in Figure 4. During a parallel or serial shift, the signal charge is transferred one pixel at a time. A full-frame readout consists of at least 2049 parallel shifts and serial readout sequences. Split parallel read out consists of 1025 shifts. Figure 5 shows the typical timing for a full frame readout. A serial readout sequence consists of at least 2088 serial shifts for the full-frame mode (20 for each serial extended region plus 2048 pixels of data from the imaging array) and 1044 (1024+20) shifts for split serial modes. The serials are static when the parallels are shifting and vice-versa. During integration, the serial clocks are normally kept running continuously to flush the serial registers and to stabilize the bias levels in the off-chip signal chain.

The timing diagram (Figure 4) is for integration under phases 1 and 2. For MPP operation, this timing is a requirement (as it is with all SITe MPP devices). For non-MPP operation this timing is also a desirable option, since the number of rows will remain the same as for MPP operation. For the users reference, typical timing for the clamp and sample signal of an external charge detection circuit are included in the output timing diagrams.