This webpage contains small-scale WFPC2 dither patterns designed to improve the rejection of detector artifacts, and/or create sub-sampled data. See the WFPC2 mosaic pattern webpage for patterns designed to increase the field-of-view for large targets. See the WFPC2 pointing patterns top page for general information about WFPC2 pointing. The following patterns are projected onto the detector pixel space in Figure 1 below. Send your pointing questions to the STScI Help Desk (help@stsci.edu).
The WFPC2-LINE is a one-dimensional dither pattern. It is really a template which can be modified within the following allowable parameter ranges, but with defaults (pattern 10 below):
Pattern_Number: ? (arbitrary integer)
Pattern_Type: WFPC2-LINE
Pattern_Purpose: DITHER
Number_Of_Points: 2-10
Point_Spacing: 0.01 - 3.0 (arcseconds)
Coordinate_Frame: POS-TARG
Pattern_Orient: ? (degrees)
Center_Pattern: ? (YES or NO)
The default WFPC2-LINE pattern produces a shift of 2.5 x 2.5 pixels on the WF chips, and 5.5 x 5.5 pixels on the PC chip:
Pattern_Number: 10
Pattern_Type: WFPC2-LINE
Pattern_Purpose: DITHER
Number_Of_Points: 2
Point_Spacing: 0.353
Coordinate_Frame: POS-TARG
Pattern_Orient: 45
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
0.249, 0.249
The default WFPC2 dither line pattern appears within APT, but cannot be modified beyond the limits above. But other one-dimensional patterns can be designed with the generic LINE Pattern Type. Some suggested patterns follow...
These two integral-pixel WFPC2-LINE patterns produce shifts of 5x5 pixels and 10x10 pixels (respectively) on the WF chips. These values are suggested because they also produce integral-pixel shifts of 11x11 pixels and 22x22 pixels (respectively) on the PC chip.
Pattern_Number: 11
Pattern_Type: WFPC2-LINE
Pattern_Purpose: DITHER
Number_Of_Points: 2
Point_Spacing: 0.704
Coordinate_Frame: POS-TARG
Pattern_Orient: 45
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
0.498, 0.498
Pattern_Number: 12
Pattern_Type: WFPC2-LINE
Pattern_Purpose: DITHER
Number_Of_Points: 2
Point_Spacing: 1.409
Coordinate_Frame: POS-TARG
Pattern_Orient: 45
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
0.996, 0.996
These two chip seam LINE patterns produce shifts of 20x20 pixels and 5x40 pixels (respectively) on the WF chips. They produce shifts of 44x44 pixels and 11x88 pixels (respectively) on the PC chip. They are designed to help reject the chip edge effects that produce noticeable "seams" between the chips. Pattern 13 shifts in both dimensions for all the chip seams, whereas pattern 14 (which extends outside Figure 1 below) shifts mostly across the WF2-WF3 boundary, if only those two chips are being used.
Pattern_Number: 13
Pattern_Type: LINE
Pattern_Purpose: DITHER
Number_Of_Points: 2
Point_Spacing: 2.817
Coordinate_Frame: POS-TARG
Pattern_Orient: 45
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
1.992, 1.992
Pattern_Number: 14
Pattern_Type: LINE
Pattern_Purpose: DITHER
Number_Of_Points: 2
Point_Spacing: 4.015
Coordinate_Frame: POS-TARG
Pattern_Orient: 82.87
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
0.498, 3.984
DITHER BOX patterns
The default WFPC2-BOX pattern has relative pixel coordinates
(0, 0), (5.0, 2.5), (7.5, 7.5), (2.5, 5.0) on the WF chips, and
(0, 0), (11.0, 5.5), (16.5, 16.5), (5.5, 11.0) on the PC chip.
It is a parallelogram pattern designed for half-pixel sampling
in both x and y on all chips. It has with overall dimensions large
enough to help reject typical detector artifacts like bad columns and
hot pixels.
Pattern_Number: 15
Pattern_Type: WFPC2-BOX
Pattern_Purpose: DITHER
Number_Of_Points: 4
Point_Spacing: 0.557
Line_Spacing: 0.557
Coordinate_Frame: POS-TARG
Pattern_Orient: 26.57
Angle_Between_Sides: 143.13
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
0.498, 0.249
0.747, 0.747
0.249, 0.498
This intermediate dither BOX pattern has relative pixel coordinates
(0, 0), (10.0, 7.5), (17.5, 17.5), (7.5, 10.0) on the WF chips, and
(0, 0), (22.0, 16.5), (38.5, 38.5), (16.5, 22.0) on the PC chip.
It is a parallelogram pattern designed for half-pixel sampling
in both x and y on all chips. It's larger overall dimensions help
reject any atypically large detector artifacts or clusters of bad columns
or hot pixels that may be more common as WFPC2 ages.
Pattern_Number: 16
Pattern_Type: BOX
Pattern_Purpose: DITHER
Number_Of_Points: 4
Point_Spacing: 1.245
Line_Spacing: 1.245
Coordinate_Frame: POS-TARG
Pattern_Orient: 36.87
Angle_Between_Sides: 163.74
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
0.996, 0.747
1.743, 1.743
0.747, 0.996
This large dither BOX pattern has relative pixel coordinates
(0, 0), (20.0, 12.5), (27.5, 27.5), (12.5, 20.0) on the WF chips, and
(0, 0), (44.0, 27.5), (60.5, 60.5), (27.5, 44.0) on the PC chip.
It is a parallelogram pattern designed for half-pixel sampling
in both x and y on all chips. It has with overall dimensions large
enough to help reject atypical detector artifacts, and also the
chip edges which otherwise create noticeable "seams" of bad pixels
between the chips. Note that the larger shifts reduce the overall
field-of-view, see Figure 2, below.
Pattern_Number: 17
Pattern_Type: BOX
Pattern_Purpose: DITHER
Number_Of_Points: 4
Point_Spacing: 2.349
Line_Spacing: 2.349
Coordinate_Frame: POS-TARG
Pattern_Orient: 32.01
Angle_Between_Sides: 154.01
Center_Pattern: NO
POS TARG equivalent: 0.000, 0.000
1.992, 1.245
2.739, 2.739
1.245, 1.992
 Figure 1: The small-scale WFPC2 dither patterns, relative to WF chip pixels. Each dither point is identified by the arbitrary Pattern Number used above. |
 Figure 2: It is important to note that the larger shifts reduce the overall field-of-view a few percent for the WF chips, but considerably more for the PC. For example, the large dither BOX (pattern 17) is shown here. |