Äîêóìåíò âçÿò èç êýøà ïîèñêîâîé ìàøèíû. Àäðåñ îðèãèíàëüíîãî äîêóìåíòà : http://zebu.uoregon.edu/~uochep/talks/talks04/si-w.pdf Äàòà èçìåíåíèÿ: Fri Mar 12 21:52:55 2004 Äàòà èíäåêñèðîâàíèÿ: Tue Oct 2 09:55:15 2012 Êîäèðîâêà: Ïîèñêîâûå ñëîâà: m 5

Silicon Tungsten Calorimetry David Strom University of Oregon

· · · ·

Design Consideration Silicon Detector Design Electrons and Noise Mechanical Design

· Timing resolution · Plans and lab activity · Si-W Mechanical Design

Si-W work ­ p ersonnel and resp onsibilities M. Breidenbach, D. Freytag, N. Graf, G. Haller,O. Milgrome SLAC Electronics, Mechanical Design, Simulation
SLAC meeting

R. Frey, D. Strom UO Si Detectors, Mechanical Design, Simulation 1

V. Radeka BNL Electronics

8 January 04 ­ David Strom ­ UO


Primary ECAL Design Requirements

· Excellent separation of 's from charged particles Efficiency > 95% for energy flow · Go o d reconstruction of ±, detection of neutral hadrons

· Reasonable EM energy resolution (< 15%/ E )

· Reconstruct 's and measure p olarization (separate , , a1, e's)

· Reconstruct Bhabhas and deconvolve luminosity sp ectra Position resolution 100µm, bias 25µm in endcap

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Secondary ECAL Design Requirements

· Excellent electron identification in jets (tag and b/c quarks)

· Partial reconstruction of b/c hadrons in jets

· Go o d impact resolution for long lived SUSY neutrals 1 cm

· Go o d background immunity ­ Bunchlet identification ­ High granularity

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SiW Design Consideration
Signal in Pad (mips) Signal in Pad (mips)

OPAL - 45 GeV Electron Lateral Shower Profiles
150

Signal in Pad (mips)

200

Signal in Pad (mips)

· Transverse shower size scales with Moli` radius ere (9mm in pure W, 16mm in pure Pb) Minimize gaps b etween layers of absorb er Use a high purity W alloy · Sample b etween 1/2 and 2/3 of X0 (1.75mm to 2.5mm of W)

Data

10

2

100

10

50

1

0

10 5 10 15 20

-1

5

10

15

20

Shower at 4 X0

Pad Number

Shower at 4 X0

Pad Number

10

2

150

10

100 1

50

0

5

10

15

20

5

10

15

20

Shower at 6 X0
Signal in Pad (mips)
200

Pad Number Signal in Pad (mips)

Shower at 6 X0

Pad Number

· Allow for detector segmentation at a fraction of the Moli`re rae dius Use 5mm pads
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10

2

150

100

10

50

1

0

5

10

15

20

5

10

15

20

Shower at 8 X0

Pad Number

Shower at 8 X0

Pad Number

4

8 January 04 ­ David Strom ­ UO

1 X0 sampling, 2.8 mm gap


Si-W Calorimeter Concept ECAL

Inner Tracker

1.25m

Rolled Tungsten

Circuit Board

Transverse Segmentation ~5mm 30 Logitudnal Samples 1/2 Energy Resolution ~15%/E
SLAC meeting

3.6 Meters 1.1-1.3 Meters

Silicon Wafers
Layer Assembly

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8 January 04 ­ David Strom ­ UO


Silicon Concept

· Readout each wafer with a single chip · Bump b ond chip to wafer · To first order cost indep endent of pixels /wafer · Hexagonal shap e makes optimal use of Si wafer · Channel count limited by p ower consumption and area of front end chip · May want different pad layout in forward region

Front End Chip

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Silicon Design Details

· DC coupled detectors · Two metal layers · Keep Si design as simple as p ossible to reduce cost · Cross talk lo oks small with current electronics design

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Electronics Design

· Chip area driven by feedback capacitor on charge integrator and 3V supply. Need 2000 MIP (8 pC) dynamic range for 500 GeV electrons. 10pF feedback capacitor Effective 16 bit dynamic range Detector · Novel design uses two different feedback capacitors · 5 to 10ns timing p ossible · Current in input transistor pulsed duty cycle < 10-3 · Exp ect p ower << 40mW/wafter
+Bias

10 pF 1pF 1V

+ -

Scale Select (1 bit)

Charge Amplifier

Charge (12 bits) + Timing (12 bits)

Threshold

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8 January 04 ­ David Strom ­ UO


Warm versus Cold Machines · Present electronics design is optimized for a warm machine. · In a cold machine a digital pip eline would b e needed for for each channel as integration over the very long bunch trains would not b e p ossible. Comparator presently foreseen for timing circuit could b e used to trigger ADC and record bunch numb er · The main impact of a cold machine would b e increased p ower consumption and complexity in the digital p ortion of the chip. ( The increased p ower consumption is a second order effect.)

Simpler warm machine electronics a go o d place to start
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8 January 04 ­ David Strom ­ UO


Si Prototyp es · Design completed Provisional grid spacing for bump-b onding
6.20 +/- 0.04 to pixels to pixels

17.50 +/- 0.04

to pixels

Bump Pad Array, v2.1 16 traces (maximum) from pixels to a typical bump pad row Each trace 0.006 wide Detail B Unit: mm Traces to bump pads, typical 8/28/03 R. Frey

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8 January 04 ­ David Strom ­ UO


Si Prototyp e prop erties ­ leakage current and noise · Radiation damage to detectors is probably dominated by neutrons, 10 â 1010/cm2 < 10nA /pixel leakage current · Exp ect typical leakage current at start of life < 1nA/pixel

· Noise from leakage current at end-of-life for 1µs sampling time (can b e adjusted ) and DC coupling scheme is < 350 electrons

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· The dynamically switchable full dynamic range only in the Very high p ower would b e to keep the noise flo or at the · Present design has noise:

feedback capacitor scheme requires the initial charge amplifier. needed in much of the electronics chain equivalent of 400 electrons.

20 - 30e/pf For most channels the value of Cinput is dominated by stray capacitance of the trace connecting the pixels to the electronics: Cinput 5.7pF(pixel) + 12pF(trace) + 10pF(amp) 30pF - 1000 electrons noise (c.f. 24,000 from MIP)

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Fitting it all together

Cooling ECAL
· Carto on of p ossible barrel calorimeter configuration · Assume heat flows along tungsten and/or copp er heat sink to co oling water (green) · Longest path for heat flow < 1.4m

Inner Tracker

1.25m

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Layout of Individual calorimeter layers:
Brazed Joints Rolled Tungsten

>3.5mm

Circuit Board

3.6 Meters 1.1-1.3 Meters Silicon

Layer Assembly

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Critical parameter: minimum space b etween tungsten layers.

Angle subtended by Moliere radius (mrad)

Config.

Radiation length 3.5mm 3.9mm 5.5mm 6.4mm

Moli`re e Radius 9mm 10mm 14mm 17mm

18 16 14 12 10 8 6 4
With copper heat sink

1.0

0.8

100% W 92.5% W +1mm gap +1mmCu

0.6

0.4

0.2

2 0 0.5 1 1.5

No copper

2

2.5

3

Gap width (mm)

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Angle subtended by Moliere radius (deg)

20

SD, Radius to calorimeter = 1.25m


Heat flow

Back of the envelop e calculation of change in temp erature: · Thermal Conductivity of W alloy 120W/(K-m) · Thermal Conductivity of Cu 400W/(K-m) Need to reduce heat to b elow 100mW/wafer. Physical mo del test in progress

temperature deg. C

20 18 2.5 mm of W 100mW 16 1.0 mm of Cu 100mW 14 1.0 mm of Cu + 2.5 mm of W at 100mW 12 2.5 mm of W 40mW 10 8 6 4 2 0

0

20

40

60

80

100

120 140 Length (cm)

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Prototyp e Tungsten Pieces · OPAL tungsten ground to size (almost more exp ensive than tungsten itself !) · Prototyp e rolled (92.5% W) lo ok fine grinding still needed) pieces (some

· Quality b etter than OPAL · 1 m long pieces p ossible · Thickness variation < 30µm

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Summary of Granularity ­ Most imp ortant figure of merit · With 92.5% W and 1 mm gap we can have a Moli` radius of ere 14 mm which has an angular size of 11 mrad at 1.25 m

provided we can keep the p ower down to 40 mW wafer

· This will b e challenging, but may b e p ossible

What ab out energy resolution
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Geant 4 simulation of energy resolution from Graham Wilson

· 1 GeV photons · 0.1 µm range cuts · 42 and 75 layers of W · Si apparently b enefits from subMIP energy dep osits ­ can we see this in a real detector?

Energy resolution at 1 GeV (per cent)

25

22.5 20

17.5 15

12.5 10 7.5 5 2.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Active material thickness (mm)

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8 January 04 ­ David Strom ­ UO


Toy Monte Carlo Studies of Timing Resolution for 30 Samples Assumptions ­ wild guesses ­ (waiting for real electronics mo del):
· Each MIP has 30 samples at random distances from the read-out chip · Threshold for timing measurement is 8,000 electrons. · Input FET has gm = 1.5mS and the noise contribution from the rest of the amplifier is equal to input FET except for the "flo or" noise. · The charge measurement has a noise flo or of either 0 or 4000 electrons · Time constant for charge measurement is 200 ns. · Time constant for the time measurement is 50 or 200 ns. · The noise in the timing and charge circuits are uncorrelated · Random 5% channel to channel variation in threshold · Random 1% event-to-event variation in threshold · Random 5% uncertainty in constants used for correction. · Reject time measurements far from mean
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Sample Timing Results
200 ns time constant, no noise flo or

Measured time (ns)

Number

300 250 200 150

1000

Entries Mean RMS

10000 -0.3855 2.194

800 100 50 0 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 Measured charge (electrons) 600

Corrected time (ns)

150 100 50 0 200 -50 400

-100 -150 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 Measured charge (electrons) 0 -20 -15 -10 -5 0 5 10 15 20 Reconstructed Time (ns)

Time versus charge for mips
SLAC meeting

30 sample average time
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8 January 04 ­ David Strom ­ UO


Including a 4000 electron noise flo or (not needed in new electronics design):
Number 600 Entries Mean RMS 10000 -0.5535 5.009 Number Entries Mean RMS 10000 0.7488E-01 1.399

1800

1600 500 1400 400

1200

1000 300 800

200

600

400 100 200

0

-20

-15

-10

-5

0

5

10 15 20 Reconstructed Time (ns)

0

-20

-15

-10

-5

0

5

10 15 20 Reconstructed Time (ns)

30 sample average 200ns time constant
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30 sample average time 50ns time constant
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8 January 04 ­ David Strom ­ UO


With no noise flo or (eg use switchable feedback capacitor) and 50ns time constant:

Number

Entries Mean RMS

10000 0.2508E-01 0.7233

2500

2000

1500

1000

500

0

-20

-15

-10

-5

0

5

10 15 20 Reconstructed Time (ns)

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8 January 04 ­ David Strom ­ UO


Practice with 6x6 1cm2 cell detectors: IR laser Prob e station
Peak voltage (mV) 500 450 400 350 300 250 200 150 100 50 0

0

5

10

15

20

25

30

35

40

45 50 Power (mW)

Depletion depth from CV curve
d(microns) 300

MIP with scintillator

250

MIP in Silicon
Corners Edges Middle

200

150

100

Scintillator

50

0

0

20

40

60

80

100

120 140 bias voltage(V)

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8 January 04 ­ David Strom ­ UO


Si-W status · Design of first silicon detectors complete Prototyp es will arrive in early '04 · Electronics design well advanced Exp ect to b e ready for submission in early '04 · Mechanical conceptual design started 1mm gap b etween layers without a copp er heat sink may b e p ossible Gap size dep ends crucially on p ower consumption

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8 January 04 ­ David Strom ­ UO


Si-W Near Term Plans · Pro duce prototyp e electronics ­ early next year · Test bump b ounding electronics to detectors in '04 · Ready for Test Beam in '05 · Confirm thermal mo del and explore b est coupling metho d of chips to absorb er · Simulation job list: ­ Optimize sampling for energy resolution ­ Compare GEANT 4 /EGS and data on Eres versus silicon thickness ­ Optimize pixel layout ­ Would more granularity help? ­ How sensitive is energy flow to Moli` e radius? er

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8 January 04 ­ David Strom ­ UO