Äîêóìåíò âçÿò èç êýøà ïîèñêîâîé ìàøèíû. Àäðåñ îðèãèíàëüíîãî äîêóìåíòà : http://zebu.uoregon.edu/~uochep/talks/talks05/ds08-05.pdf Äàòà èçìåíåíèÿ: Thu Sep 1 20:15:23 2005 Äàòà èíäåêñèðîâàíèÿ: Tue Oct 2 10:38:46 2012 Êîäèðîâêà: Ïîèñêîâûå ñëîâà: http www.astronomy.ru forum index.php topic 4644.0.html

D. Strom With apologies to C. Baltay August 2005

Monolithic CMOS Pixel Detectors for ILC Vertex Detection

C. Baltay, W. Emmet, H. Neal, D. Rabinowitz Yale University Jim Brau, O. Igonkina, N. Sinev, D. Strom University of Oregon


ILC Vertex Detector Design
125 mm x 22 mm CCD s
60 mm

Monolithic CMOS Pixel Detectors
Layer Radius Cm 1 2 3 4 5 1.2 2.4 3.6 4.8 6.0 Total Length Cm 5.0 25.0 25.0 25.0 25.0 8x1 8x2 12x2 16x2 20x2 No of Chips Chip Size Cm 5.0x1.2 12.5x2.2 12.5x2.2 12.5x2.2 12.5x2.2
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Total number of chips 120

Total Number of Pixels 1.25 x 1010


Time Structure for the Cold Design

Background Calculation: At 1.5 cm from Interaction Point with 3 Tesla field expect 0.03 hits /mm2/bunch crossing Will use this number for the entire detector

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Conventional CCD's Not Well Suited for This Application
· Consider SLD type CCD's with 20µ x 20µ pixels
22 mm x 125 mm = 2750 mm with 6.9 x 106 pixels/CCD
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· Readout time at 25 MHz is 275 msec
May be can push to 50 MHz readout or divide CCD into several readout sections

Can readout in 200 msec between pulse trains · Occupancy, integrating over 2820 bunches in a pulse train
0.03 hits/mm2/bunch x 2820 bunches x 3 pixels/hit
= 250 pixels hit/mm
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or 10% of the pixels have a hit (occupancy)

· SLD Experience ­ occupancy of 10-3 or 2.5 hits/mm2 are maximum we could handle! Occupancy too high by factor of ~ 100!!
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Monolithic CMOS Pixel Detectors
What are they?
· New CMOS technology makes pixels as small as 5 µ x 5 µ possible
·

Each pixel has its own intelligence (electronics) under the pixel

· Unlike CCD's, all pixels are NOT read out in a raster scan · Reads out x,y coordinates only of pixels with hit (i.e., exceeding an adjustable threshold) at 25 MHz · Monolithic design ­ photosensitive detector pixel array and read out electronics for each pixel on the same piece of silicon ­ can be quite thin (few x 100 µ?)


Advantages over CCD's
· Significantly faster read out. Typical occupancy of vertex detector at e+e- collider ~ 10-3 1000 times faster read out! (Read only hit pixels!) · Potentially more radiation hard · Small 5 µ x 5 µ pixels allow good resolution

Advantages over hybrid pixel devices used at the LHC
· Do not need bump bonding of pixel detector to electronics layer · Allows much smaller pixels
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First Readout Scheme Considered:
· Bunches within a train separated by 337 nano sec! · Expected background
~ 0.03 hits/mm2/bunch

· Can NOT integrate over 2820 bunches ­ occupancy too high! · Plan to read out each bunch in 337 n sec! · Divide each 22 mm x 125 mm device into 25 regions (22 mm x 5 mm = 110 mm2 each) with a read out for each region · Expect .03 hits/mm2/bunch x 110 mm2 ~ 3 hits per bunch in each read out region · At 25 MHz, can read out average of 3 hits/bunch in 120 n sec, comfortably below the 337 n sec bunch spacing. This allows room for fluctuations in the number of hits/bunch · There can be buffering in each pixel read out circuit so that larger fluctuations can be tolerated as long as the average rate can be handled.

Problem ­ Electromagnetic Interference maybe too high for readout during Pulse train!

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· During the past year, working with SARNOFF we developed a conceptual design that:
­ we believe will work for an ILC Vertex Detector ­ that SARNOFF believes they can build.

Present Conceptual Design

· Plan to integrate over pulse train and readout during 200 msec between trains to avoid EMI (Electromagnetic Interference) during train.
­ Occupancy would be too high ­ BUT ­ for each hit, readout x,y, intensity, AND time of hit (time to better than 300 nsec precision effectively tagging each hit with its bunch crossing number)

­ In analyzing Vertex detector data look only at hits which occurred in the same single bunch crossing Occupancy ~ 10-6 or 0.03 hits/mm2!!
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Present Conceptual Design (Continued)
· Accomplish this with a Hierarchical Design Approach. Each device will have two separate sensitive pixel arrays with its own electronic logic under each pixel ­ Big Pixel (Macro Pixel or High Speed) Array
· 50µ x 50µ pixels · Triggers on hits above threshold · Records time of hit

­ Small Pixels (Micro Pixel or High Resolution) Array
· 5µ x 5 µ Pixels · Addressable, random access array · Records intensity of hit (3 digit resolution)
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Monolithic CMOS Pixel Detectors
Big Pixels 50µ x 50µ

Small Pixels 5 µ x 5µ

Two active particle sensitive layers: Big Pixels ­ High Speed Array ­ Hit trigger, time of hit Small Pixels ­ High Resolution Array ­ Precise x,y position, intensity

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Array Designs
High-speed arrays High-resolution arrays

Designed for quick response.
­ Threshold detection only. ­ Large pixels (~50 x 50 µm).

Designed for resolution and
querying.
­ Smaller pixel size (~5 x 5 µm). ­ Random access addressability. ­ Records intensity.

Transmits X,Y location and
time stamp of impact.

Provides intensity

information only for pixel region queried.

Contact Pads

Pixel Array

Contact Pads

Pixel Array

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Hierarchical Array Operation
· Particles from any particular bunch crossing traverse both the Big and the Small pixel arrays · The Big Pixels which are hit store the time information (i.e. bunch number) in a 13 bit digital memory located under the area of the Big Pixel. The hit number counter is advanced after each hit. Up to 4 hit times can be stored under each pixel
(The probability of a Big Pixel being hit more than 4 times in a pulse train is 10-3)

· The Small Pixels which are hit store the analog signal charge locally in the area under each pixel for the duration of a pulse train
(Probability of two hits in the same Small Pixel in a pulse train is 1%)
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Hierarchical Array Operation (continued)
· Readout starts in the 200 msec gap after each train
­ x,y coordinates and intensity from Small Pixels that are hit, with time stamp from the corresponding Big Pixel ­ A small fraction of the hits will have ambiguity in time, i.e., more than one time stamp (This will increase the occupancy by 30% above 10-6) ­ Both the Big Pixel and the Small Pixel arrays will be reset before the next pulse train

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Macro Pixel Array Architecture
VDD

Macro pixel Vertical Decoder Macro pixel Vertical Decoder

13 x 4 F/F Array

Row Line Pixel

Reset PD

Comparator _ + Vth

Latch Enable

F/F F/F F/F F/F F/F F/F F/F F/F F/F

F/F F/F F/F F/F F/F F/F F/F F/F

Counter

F/F F/F F/F

50 um x 50um Column Data Bus
13 13 13 13 13 13 13 13

D12 D10 D11

D0** D1

Macro Pixel

MUX Macro Pixel Column Select Logic Bunch Counter Timing Controller Digital Out

Column Data Bus (Bunch Counter, 1~3000)

**D0 serves for parity check

· As a local digital memory to store the time stamp, F/F's are used. To express 3000 bunches, 12 bits are needed and 13th bit is for checking the parity. Since average multiple impact probability per pixel is assumed to be 4, 13 (H) x 4 (V) F/F's are needed in this architecture. · When a particle impacts, a pixel's signal rises above the threshold level and comparator out switches from `1' to `0', enabling the F/F's to latch the time stamp data supplied by the global bunch counter. When the data is latched, the pixel is reset. · If next particle impacts the same location, comparator out enables next set of F/F's to preserve the previous time stamp data. This is implemented using a counter which increments the row address of the F/F array. · Time stamp information is read out in the random access mode from the pixels of interest which stored nonzero time stamp data.

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Micro Pixel Array Architecture
Micro pixel Vertical Decoder and Driver
VDD Reset

Row Line Pixel

Q1 Q2 Q3 Out

Row Select

(5um x 5um) Column Signal Bus CDS and MUX Micro Pixel Column Select Logic Timing Controller Amp ADC Micro Pixel Out

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Expected Occupancy and Hit Rates

· Estimate for a typical 22 mm x 125 mm chip using 0.03 hits/mm2/bunch crossing (this is conservative for the outer layers). Assume that each hit will put charge above threshold into, on the average, 3 Small Pixels. · Each chip will have
22 mm x 125 mm = 2750 mm 1.1 x 106 Big Pixels 1.1 x 108 Small Pixels
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· Integrating over 2820 bunches in a pulse train we expect
0.03 hits/mm2/bunch x 2820 bunches 85 hits/mm ~ 20% probability of a hit in a Big Pixel
(~ 4% probability of 2 hits, 0.8% 3 hits, 0.16% 4 hits)
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6 x 10-3 occupancy in Small Pixels per pulse train 2 x 10-6 occupancy in Small Pixels per bunch crossing

· Effective Occupancy ~ 2 x 10-6!!
Total number of hits per 22 mm x 125 mm chip 7 x 105 Small Pixel hits/pulse train Readout time 7 x 105 hits/25 MHz ~ 28 msec + some overhead
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1.

Other Comments & Issues
Thickness
Present state of the art is 100 to 200 µ total thickness for the sum of the Macro and Micro Arrays. Could improve with some R&D to maybe 50 µ. Present estimate 1.8 watts/chip could improve with R&D.

2. 3.

Power Consumption

Fabrication Issues ­ two possible approaches

a) Both Macro and Micro Pixel Arrays fabbed in a single process on the same piece of silicon. b) Macro and Micro Pixel Arrays fabbed in separate processes, then bonded together. No electrical connections needed between Macro and Micro Pixels in active area of detector ­ all connections are at one end of the chip. Present layout tooling allow 21 mm x 21 mm devices ­ will have to learn how to "stitch" these areas together to make our size devices. They don't think this is a problem but they have not actually done it yet in CMOS process. a) The first prototypes will probably be 5 mm x 5 mm devices with the readout logic on a separate chip. b) In the final 22 mm x 125 mm active area device the readout logic can be on the same chip, at one end, making the actual device 22 mm x 130 mm long. Output connections will be at one end (away from interaction point).
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4.

Stitching

5.

First Prototype


Statement of work
Task-1 : Design and layout the micropixel (Sarnoff) Task-2 : Design and layout the macropixel (Sarnoff) Task-3 : Fabricate the test chips using MOSIS shuttle (Sarnoff) Task-4 : Particle bombardment on test chip (Yale/Oregon) Task-5 : Perform testing on test chip (Yale/Oregon w/ consulting from Sarnoff) Task-6 : Summarize data (Yale/Oregon/Sarnoff) Task-7 : Write report (Yale/Oregon/Sarnoff)

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Program Plan

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Estimated ROM Cost

The estimated ROM for this phase is : $260,000

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