Документ взят из кэша поисковой машины. Адрес оригинального документа : http://zebu.uoregon.edu/~uochep/talks/talks06/sinev10-06.pdf Дата изменения: Thu Dec 7 23:35:28 2006 Дата индексирования: Tue Oct 2 11:27:56 2012 Кодировка: Поисковые слова: m 5

Chronopixel development status
Nick Sinev, University of Oregon, On behalf of: C. Baltay, W.Emmet, H.Neal, D.Rabinovich ­ Yale University, J.Brau, O.Igonkina, D.Strom ­ University of Oregon

1


SiD Vertex Layout
5 barrel layers 4 end disks

SiD00

R [cm]

5 Tesla

Design drivers: Smallest radius possible Clear pair background

Role:

Seed tracks & vertexing Improve forward region

Z= 6.25cm Z [cm]

2


SiD Vertex Detector
BARREL
100 sensors 1750 cm2

FORWARD
288 sensors 2100 cm2

3


4


Macropixel Block Diagram

Bias
SF_OUT

Detector Vref RESET RDCLK ROW _SEL Timing Logic

Comparator Bias Write 14x4 Memory Array

Counter

Decoder

4

14

I/O Interface

14

DIO(13:0)

Y1/Y2 MINIT Empty

5


Read Noise
Minimum ionizing particle leaves 88e- /micron in epitaxial layer
15 um thick epi layer 1% inefficiency threshold ­ 375 e-, 50% hit sharing ­ 188 e-, noise = ј x 188 = 47 e-

Readout noise scales with pixel capacitance: with 12 m depletion depth it is 22 fF for 50x50 m pixels and 3.5 fF for 20x20 m pixels. Electronics noise estimation for 3.5 fF ­ 32 e6


Power Consumption
Main power consumer is analog part (amplifier + comparator). However, we do not need to keep it all time on. Current estimation for 50x50 m design (0.25 m technology) 15mW/mm2 (without taking into account duty cycle) for analog part and 0.05 mW/mm2 for digital part. Assuming duty cycle for analog parts as 1/100 we get ~0.16 mW/mm2. By conservative estimates power per unit of device area will not change by going to smaller pixel size with more advanced technology (goal ­ 0.045m feature size by 2010). This is because reduction in capacitance allows smaller current in amplifier. So, we expect ~ 0.16mW/mm2 x 2500 mm2 chip = 0.4 W / chip.

7


Power Dissipation Analysis
Compo ne nt Detec tor Ana lo g Compa rato r Sub_to ta l Timing Lo gic Counte r/ Decoder D igita l Me m. A rra y IO Inter face Sub_to ta l Tota l Be for e O ptimi zed Power D iss ipat io n O ptimi zat io n 9.9uW 27.0uW 36.9uW 0.05uW 0.07uW ~ 0uW 0.01uW 0.13uW 37.03uW 11.7uW 35.1uW 46.8uW

8


SARNOFF Response to Question on Future Technology Roadmap: Macropixel size estimation vs. Mixed-signal Process Technologies
Pi xel Pi tch 50um Year Avail able 2002 2004 2005 2007 2009

40um

30um

20um 15um 10um Min. Fea ture Size 0.18um 1.8V/3.3V 45nm 0.13um 90nm 65nm 1.2V/2.5V/3.3V 1.2V/2.5V 1.0V/1.2V/2.5V 0.8V/1.0V/1.2V

9


CONCLUSION
Completed chronopixel design
645 transistors Spice simulation verifies design TSMC 0.18 um -> 40-50 um pixel

Next phase under consideration
Complete design of macro pixel Deliverable ­tape out for foundry

Future
Fab 50 um pixel chip Then, 10-15 um pixel
10