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1. http://www.mrao.cam.ac.uk/projects/OAS/pmwiki/uploads/MROIDelayLine.DocMan/FDR_Documentation_List.pdf
Documentation for Delay Line Final Design Review - 12 Feb 2008 Notes: Anything marked in Status as [TBU] is definitely `To Be Updated' `Expected Date' refers to the expected date of release where this is likely to be different from the due date. ... TBU] INT-406-VEN-0112 MF/RCB/DMAW/EBS 22 Jan 08 22 Jan 08 Released. ... MF/XS/DMAW MF MF MF MF/XS/DMAW 22 Jan 08 29 Jan 08 Yet to be drafted 22 Jan 08 22 Jan 08 Yet to be drafted 22 Jan 08 22 Jan 08 Released. ... Document No. ...
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Ссылки http://www.mrao.cam.ac.uk/projects/OAS/pmwiki/uploads/MROIDelayLine.DocMan/FDR_Documentation_List.pdf -- 57.6 Кб -- 14.01.2008
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2. http://www.mrao.cam.ac.uk/projects/aavp/posters/daSilva_AAVP-Cambridge2010.pdf
... The design employs a differential structure. ... The input is adapted to 100 differential, and the outputs use standard Low Voltage Differential Signaling (LVDS). ... T/H SINGLE T/H Single Input T/H Single Output 1.35 0.15 0.2 T/H DIFFERENTIAL Input T/H Output T/H 0.1 1.3 0.05 volts volts Figure 5: Digital part and digital gate 0 1.25 -0.05 -0.1 1.2 Integrated Test System A test system is integrated on chip to evaluate the transmission to the data acquisition card (fig: 7). ...
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Ссылки http://www.mrao.cam.ac.uk/projects/aavp/posters/daSilva_AAVP-Cambridge2010.pdf -- 1772.7 Кб -- 06.12.2010
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. Number . Task . Pri . Author . Created By Tool . Created On . Modified On . Completed . Modified By . Assigned To . Link To . Magic . Description
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Ссылки http://www.mrao.cam.ac.uk/~nima/_vti_pvt/_x_todo.htm -- 1.5 Кб -- 06.02.2006
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