Документ взят из кэша поисковой машины. Адрес оригинального документа : http://lib.sinp.msu.ru/static/tutorials/52_p4.pdf Дата изменения: Fri Nov 28 16:48:02 2008 Дата индексирования: Sun Apr 10 22:22:43 2016 Кодировка:

4 (DSP) ADSP2181". .. 1. , 1.0. AD21XX. 1.1. ADSP2181 Data Sheet. ADSP2181. 1.2. ADSP2100 Family User's Manual. . . . . 1.3. AD1847 Data Sheet. / AD1847. / AD1847. 1.4. EZKIT Lite Reference Manual. EZKIT Lite. 1.5. ADSP2100 Family. Assembler Tools & Simulator Manual. I/O Operations, SERIAL PORTS. 2. . 2.1. MEANDR.DSP, . . 2.2. MEANDR.DSP , : 1 - , 2, - .
61


: 0 0.5 ( , -1..1) 2 - ( , ..). ( 1%): 25%..75% ( 1%): 5 ( 1%): 13 2.3. . . . 2.4. EZKIT-Lite . 2.5. 0.01%. "fractional" () "", . 2.3, 2.4.

3. . 3.0. . , , H:, LAB2. H: LAB2, J:. , H:\LAB2\. 3.1. sim2181 -a ezkit_lt -e - . HELP-. :
62


-

Program Memory Data Memory Computational Registers SPORT Registers

3.2. Norton Commander, NE. : asm21 - -2181 : ld21 - -a ezkit_lt -e - -x -g . 3.3. EZKIT Lite -, Windows. Windows win. 4. : . , , , . , , . 5. . 5.1. ? ? 6. .
63


{******************************************************** ********* * * This sample program is organized into the following sections: * * Assemble time constants * Interrupt vector table * ADSP 2181 intialization * ADSP 1847 Codec intialization * Interrupt service routines ********************************************************* *********

.module/RAM/ABS=0 loopback;

{******************************************************** ********* * * Assemble time constants * ********************************************************* ********* .const .const .const .const .const .const .const .const .const .const .const .const .const .const .const .const .const IDMA= BDMA_BIAD= BDMA_BEAD= BDMA_BDMA_Ctrl= BDMA_BWCOUNT= PFDATA= PFTYPE= SPORT1_Autobuf= SPORT1_RFSDIV= SPORT1_SCLKDIV= SPORT1_Control_Reg= SPORT0_Autobuf= SPORT0_RFSDIV= SPORT0_SCLKDIV= SPORT0_Control_Reg= SPORT0_TX_Channels0= SPORT0_TX_Channels1= 64 0x3fe0; 0x3fe1; 0x3fe2; 0x3fe3; 0x3fe4; 0x3fe5; 0x3fe6; 0x3fef; 0x3ff0; 0x3ff1; 0x3ff2; 0x3ff3; 0x3ff4; 0x3ff5; 0x3ff6; 0x3ff7; 0x3ff8;


.const .const .const .const .const .const .const

SPORT0_RX_Channels0= SPORT0_RX_Channels1= TSCALE= TCOUNT= TPERIOD= DM_Wait_Reg= System_Control_Reg= rx_buf[3]; tx_buf[3];

0x3ff9; 0x3ffa; 0x3ffb; 0x3ffc; 0x3ffd; 0x3ffe; 0x3fff; /* Status + L data + /* Cmd + L data + R

.var/dm/ram/circ R data */ .var/dm/ram/circ data */ .var/dm/ram/circ .var/dm - wrk } .var time; .var time_max;

init_cmds[13]; stat_flag; { Status: 1 - init, 0

.var/circ meandr_values[4]; .init time: 0; .init meandr_values: -16384, 5,16384, 5;

.init tx_buf:0xc000, 0x0000, 0x0000; /* Initially set MCE */ .init init_cmds: 0xc002, { Left input control reg b7-6: 0=left line 1 1=left aux 1 2=left line 2 3=left line 1 post-mixed loopback b5-4: res b3-0: left input gain x 1.5 dB } 0xc102, { Right input control reg b7-6: 0=right line 1 1=right aux 1 2=right line 2 3=right line 1 post-mixed loopback b5-4: res b3-0: right input gain x 1.5 dB } 0xc288, { left aux 1 control reg b7 : 1=left aux 1 mute 65


b6-5: res b4-0: gain/atten x 1.5, 08= 0dB, 00= 12dB } 0xc388, {

right aux 1 control reg : 1=right aux 1 mute b6-5: res b4-0: gain/atten x 1.5, 08= 0dB, 00= 12dB } 0xc488, { left aux 2 control reg b7 : 1=left aux 2 mute b6-5: res b4-0: gain/atten x 1.5, 08= 0dB, 00= 12dB } 0xc588, { right aux 2 control reg b7 : 1=right aux 2 mute b6-5: res b4-0: gain/atten x 1.5, 08= 0dB, 00= 12dB } 0xc680, { left DAC control reg b7 : 1=left DAC mute b6 : res b5-0: attenuation x 1.5 dB } 0xc780, { right DAC control reg b7 : 1=right DAC mute b6 : res b5-0: attenuation x 1.5 dB } 0xc85c, { data format register b7 : res b5-6: 0=8-bit unsigned linear PCM 1=8-bit u-law companded 2=16-bit signed linear PCM 3=8-bit A-law companded b4 : 0=mono, 1=stereo b0-3: 0= 8. 1= 5.5125 2= 16. 3= 11.025 4= 27.42857 5= 18.9 6= 32. 66 b7


16.9344 MHz 0xc909,

7= 8= 9= a= b= c= d= e= f= (b0) : { b3 }

22.05 . 37.8 . 44.1 48. 33.075 9.6 6.615 0=XTAL1 24.576 MHz; 1=XTAL2

0xca00,

0xcc40, per frame

{ pin control reg b7 : logic state of pin XCTL1 b6 : logic state of pin XCTL0 b5 : master - 1=tri-state CLKOUT slave - x=tri-state CLKOUT b4-0: res } { miscellaneous information reg b7 : 1=16 slots per frame, 0=32 slots b6 : 1=2-wire system, 0=1-wire system b5-0: res } { digital mix control reg b7-2: attenuation x 1.5 dB b1 : res b0 : 1=digital mix enabled

interface configuration reg b7-4: res : 1=autocalibrate b2-1: res b0 : 1=playback enabled }

0xcd00;

} ********************************************************* ******** * * Interrupt vector table * ********************************************************* ********* jump start; rti; rti; rti; {00: reset } rti; rti; rti; rti; {04: IRQ2 } rti; rti; rti; rti; {08: IRQL1 } rti; rti; rti; rti; {0c: IRQL0 } 67


jump next_tx; rti; rti; jump input_samples; rti; rti; jump irqe; rti; rti; rti; rti; rti; rti; rti; rti; IRQ1 } IRQ0 } rti;

rti; rti; rti; rti; rti;

{10: SPORT0 tx } {14: SPORT1 rx } {18: IRQE } {1c: BDMA } {20: SPORT1 tx or {24: SPORT1 rx or

rti; rti; rti;

rti; rti; rti; rti; {28: timer } rti; rti; rti; rti; {2c: power down } ********************************************************* ******** * * ADSP 2181 intialization * ********************************************************* ********* start: i0 = ^rx_buf; l0 = %rx_buf; i1 = ^tx_buf; l1 = %tx_buf; i3 = ^init_cmds; l3 = %init_cmds; i4 = ^meandr_values; l4 = %meandr_values; m1 = 1; m5 = 1; { DAC variables init } ar = dm (i4,m5); dm (tx_buf+1) = ar; { DAC1 value } dm (tx_buf+2) = ar; { DAC2 value } ar = dm (i4,m5); dm (time_max) = ar; {====== S E R I A L PORT #0 STUFF ============} ax0 = b#0000001010000111; dm (SPORT0_Autobuf) = ax0; { |||!|-/!/|-/|/|+- receive autobuffering 0=off, 1=on |||!| ! | | +-- transmit autobuffering 0=off, 1=on |||!| ! | +---- | receive m? |||!| ! | | m1 |||!| ! +------- ! receive i? |||!| ! ! i0 |||!| ! ! |||!| +========= | transmit m? |||!| | m1 |||!+------------ ! transmit i? 68


|||! |||! |||+============= control bit ||+-------------|+--------------control bit +----------------

! i1 ! |BIASRND MAC biased rounding 0 | CLKODIS CLKOUT disable 0 }

ax0 = 0; ax0 = 0;

{

dm (SPORT0_RFSDIV) = ax0; RFSDIV = SCLK Hz/RFS Hz - 1 } dm (SPORT0_SCLKDIV) = ax0; { SCLK = CLKOUT / (2 (SCLKDIV + 1) } dm (SPORT0_Control_Reg) = | number of bit per word - 1 | = 15 | | ! 0=right just, 0-fill; ! 2=compand u-law; 3=compand receive framing logic 0=pos, transmit data valid logic RFS 0=ext, 1=int multichannel length 0=24, 1=32 | frame sync to occur this | cycle before first bit | | ISCLK 0=ext, 1=int multichannel 0=disable,

ax0 = b#1000011000001111; ax0; { multichannel ||+--/|!||+/+---/ ||| |!||| ||| |!||| ||| |!||| ||| |!||+====== 1=right just, signed ||| |!|| A-law ||| |!|+------1=neg ||| |!+-------0=pos, 1=neg ||| |+========= ||| +---------words ||+-------------number of clock || || || |+--------------+---------------1=enable}

{ non-multichannel |||!|||!|||!+---/ | number of bit per word - 1 |||!|||!|||! | = 15 |||!|||!|||! | |||!|||!|||! | 69


|||!|||!|||+===== just,signed |||!|||!||+-----A-law |||!|||!|+------1=neg |||!|||!+-------1=neg |||!|||+========= |||!||+---------|||!|+----------data,1=FS in sync |||!+-----------|||+============= data,1=FS in sync ||+-------------|+--------------+---------------1=enable }

!0=righ just,0-fill;1=right ! 2=compand u-law; 3=compand receive framing logic 0=pos, transmit framing logic 0=pos, RFS 0=ext, 1=int TFS 0=ext, 1=int TFS width 0=FS before TFS 0=no, 1=required RFS width 0=FS before RFS 0=no, 1=required ISCLK 0=ext, 1=int multichannel 0=disable,

ax0 = b#0000000000000111; dm (SPORT0_TX_Channels0) = ax0 { ^15 00^ transmit word enables: channel # == bit # } ax0 = b#0000000000000111; dm (SPORT0_TX_Channels1) = ax0; { ^31 16^ transmit word enables: channel # == bit # } ax0 = b#0000000000000111; dm (SPORT0_RX_Channels0) = ax0; { ^15 00^ receive word enables: channel # == bit # } ax0 = b#0000000000000111; dm (SPORT0_RX_Channels1) = ax0; { ^31 16^ receive word enables: channel # == bit # } {=== S Y S T E M AND MEMORY STUFF ======} ax0 = b#0000111111111111; dm (DM_Wait_Reg) = ax0; { |+-/+-/+-/+-/+-/- ! IOWAIT0 || | ! | ! || | ! | ! || | ! +------ | IOWAIT1 || | ! | || | ! | || | +--------- ! IOWAIT2 || | ! || | ! || +------------ | IOWAIT3 || | 70


|| |+=============== | | +---------------ax0 = b#0001000000000000; (System_Control_Reg) = ax0; { +-/!||+-----/+-/states | !||| | !||| | !||+---------| !|| | !|| | !|| | !|| | !|| | !|| | !|+----------0=FI, FO, IRQ0, | !+-----------0=disabled | +============= 0=disabled +----------------

| ! DWAIT ! ! 0 dm

}

| program memory wait |0 | 0 0 0 0 0 0 0 SPORT1 1=serial port, IRQ1,.. SPORT1 1=enabled, SPORT0 1=enabled, 0 0 0

}

ifc = b#00000011111111; { clear pending interrupt } nop; icntl = b#00000; { ||||+- | IRQ0: 0=level, 1=edge |||+-- | IRQ1: 0=level, 1=edge ||+--- | IRQ2: 0=level, 1=edge |+---- 0 |----- | IRQ nesting: 0=disabled, 1=enabled } mstat = b#1000000; { ||||||+- |Data register bank select |||||+-- |FFT bit reverse mode (DAG1) ||||+--- |ALU overflow latch mode, 1=sticky |||+---- |AR saturation mode, 1=saturate, 0=wrap ||+----- | MAC result, 0=fractional, 1=integer |+------ | timer enable 71


+------- | GO MODE

}

********************************************************* ******** * * ADSP 1847 Codec intialization * ********************************************************* ********* { clear flag } ax0 = 1; dm(stat_flag) = ax0;

{

enable transmit interrupt } imask = b#0001000000; { |||||||||+ | timer ||||||||+- | SPORT1 rec or IRQ0 |||||||+-- | SPORT1 trx or IRQ1 ||||||+--- | BDMA |||||+---- | IRQE ||||+----- | SPORT0 rec |||+------ | SPORT0 trx ||+------- | IRQL0 |+-------- | IRQL1 +--------- | IRQ2} ax0 = dm (i1, m1); { start interrupt } tx0 = ax0; check_init: ax0 = dm (stat_flag); { wait for entire init } af = pass ax0; { buffer to be sent to } if ne jump check_init; { the codec } ay0 = 2; check_aci1: ax0 = dm (rx_buf); { once initialized, wait for codec } ar = ax0 and ay0; { to come out of autocalibration } if eq jump check_aci1; { wait for bit set } check_aci2: ax0 = dm (rx_buf); { wait for bit clear } ar = ax0 and ay0; if ne jump check_aci2; 72


idle; ay0 = 0xbf3f; { unmute left DAC } ax0 = dm (init_cmds + 6); ar = ax0 AND ay0; dm (tx_buf) = ar; idle; ax0 = dm (init_cmds + 7); { unmute right DAC } ar = ax0 AND ay0; dm (tx_buf) = ar; idle; ifc = b#00000011111111; { clear any pending interrupt } nop; imask = b#0001010000; { enable tx0 & irqe interrupt } { |||||||||+ | timer ||||||||+- | SPORT1 rec or IRQ0 |||||||+-- | SPORT1 trx or IRQ1 ||||||+--- | BDMA |||||+---- | IRQE ||||+----- | SPORT0 rec |||+------ | SPORT0 trx ||+------- | IRQL0 |+-------- | IRQL1 +--------- | IRQ2} { wait for interrupt and loop forever } talkthru: idle; jump talkthru; {******************************************************** ******** * Interrupt service routines ********************************************************* ******** receive interrupt is not used} input_samples: rti; {--------------------------------------------------------------transmit interrupt used for Codec initialization, and Data generating ---------------------------------------------------------------} next_tx: ena sec_reg; ar = dm (stat_flag); ar = pass ar; if eq jump next_data; { init Codec } ax0 = dm (i3, m1); { fetch next control word and } 73


dm (tx_buf) = ax0; { place in transmit slot } ax0 = i3; ay0 = ^init_cmds; ar = ax0 - ay0; if gt rti; { rti if more control words still waiting } ax0 = 0xaf00; { else set done flag and } dm (tx_buf) = ax0; { remove MCE if done initialization } ax0 = 0; dm (stat_flag) = ax0; { reset status flag } rti; next_data: ay0 = dm (time); ay1 = dm (time_max); ar = ay0+1; af = ay1-ar; if gt jump calc; { change meandr variables } ar = dm (i4,m5); dm (tx_buf+1) = ar; dm (tx_buf+2) = ar; ar = dm (i4,m5); dm (time_max) = ar; ar = 0; { reset time } calc: dm (time) = ar; rti; 0 { INTERRUPT button service - indicator FL1 flashing} irqe: toggle fl1; rti; .endmod;

74