Патенты сотрудников кафедры и лаборатории

1. Chen Jian-Guo, Mazurenko I.L., Meng-Lin Yu, Petyushko A.A. Preamble detection using vector processors US Patent 9184787. November 10, 2015. www.google.com/patents/US9184787
2. Бабин Д.Н., Мазуренко И.Л., Холоденко А.Б., Пархоменко Д.В., Михайлов Д.С., Уранцев А.В. Способ определения текущего состояния глаз оператора при контроле бодрствования.
   Патент РФ 2563091, 20.09.2015. 2563091.pdf
3. Aliseychik P.A., Evers Petrus Sebastiaan Adrianus Daniel, Parfenov D.V., Filippov A.N., Zaytsev D.V. Program module applicability analyzer for software development and testing for multi-processor environments. United States Patent: 9,043,770, May 26, 2015. http://patft.uspto.gov/[...]
4. Petyushko A.A., Bolotov A.A., Han Yang, Mazurenko I.L., Kholodenko A.B., Zaytsev D.V., Parfenov D.V. Method for selecting a LDPC candidate code. United States Patent: 9,037,944, May 19, 2015. http://patft.uspto.gov/[...]
5. Zaytsev D.V., Parfenov D.V., Han Yang, Mazurenko I.L., Babin D.N. Efficient way to construct LDPC code by comparing error events using a voting based method. United States Patent: 8,977,925, March 10, 2015. http://patft.uspto.gov/[...]
6. Sokolov A.P., Gasanov E.E., Neznanov I.V., Aliseychik P.A., Panteleev P.A. Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards. United States Patent: 8,938,654, January 20, 2015. http://patft.uspto.gov/[...]
7. Babin D.N., Parkhomenko D.V., Mazurenko I.L., Parfenov D.V., Filippov A.N. Double precision approximation of a single precision operation. United States Patent: 8,924,447, December 30, 2014. http://patft.uspto.gov/[...]
8. Shutkin Yu.S., Neznanov I. V., Sokolov A. P., Panteleev P. A., Gasanov E. E. Optimization of data processors with irregular patterns. United States Patent: 8,923,413, December 30, 2014. http://patft.uspto.gov/[...]
9. Aliseychik P.A., Gasanov E. E., Neznanov I. V., Panteleev P. A., Sokolov A. P. Packet router having a hierarchical buffer structure. United States Patent: 8,923,315, December 30, 2014. http://patft.uspto.gov/[...]
10. Irmatov A.A., Buryak D.Yu., Cherdakov D.V., Lee D.S. Face detection method and apparatus. United States Patent: 8,885,943, November 11, 2014. http://patft.uspto.gov/[...]
11. Shutkin Yu.S., Gasanov E. E., Neznanov I. V., Sokolov A. P., Panteleev P. A. No-delay microsequencer. United States Patent: 8,868,890, October 21, 2014. http://patft.uspto.gov/[...]
12. Shutkin Yu.S., Aliseychik P.A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Panteleev P. A. Two-pass linear complexity task scheduler. United States Patent: 8,850,437, September 30, 2014. http://patft.uspto.gov/[...]
13. Sokolov A. P., Panteleev P. A., Gasanov E. E., Neznanov I. V., Shutkin Yu.S. L-value generation in a decoder. United States Patent: 8,842,784, September 23, 2014. http://patft.uspto.gov/[...]
14. Bolotov A.A., Letunovskiy A.A., Mazurenko I.L., Ivanovic L.D., Zhang Fan. Dynamically controlling the number of local iterations in an iterative decoder. United States Patent: 8,832,532, September 9, 2014. http://patft.uspto.gov/[...]
15. Mazurenko I. L., Babin D.N., Parfenov D.V., Petyushko A. A., Markovic A. Time-domain acoustic echo control. United States Patent: 8,824,667, September 2, 2014. http://patft.uspto.gov/[...]
16. Petyushko A. A., Babin D.N., Shaw D.G., Mazurenko I. L., Aliseychik P.A. Fast echo gain change detection. United States Patent: 8,817,970, August 26, 2014. http://patft.uspto.gov/[...]
17. Mazurenko I. L., Babin D.N., Parkhomenko D.V., Petyushko A. A., Parfenov D.V. Stochastic vector based network echo cancellation. United States Patent: 8,804,946, August 12, 2014. http://patft.uspto.gov/[...]
18. Mazurenko I.L., Petyushko A.A., Meng-Lin Yu, Chen Jian-Guo. Chunk-based double-dwell preamble detection. United States Patent: 8,804,672, August 12, 2014. http://patft.uspto.gov/[...]
19. Mazurenko I. L., Letunovskiy A.A., Markovic A., Parfenov D.V., Petyushko A. A. Intra-mode prediction for a video transcoder. United States Patent: 8,780,983, July 15, 2014. http://patft.uspto.gov/[...]
20. Gasanov E. E., Panteleev P. A., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Radix-4 viterbi forward error correction decoding. United States Patent: 8,775,914, July 8, 2014. http://patft.uspto.gov/[...]
21. Panteleev P. A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Variable parity encoder. United States Patent: 8,775,893, July 8, 2014. http://patft.uspto.gov/[...]
22. Letunovskiy A.A., Lyalin I.V., Markovic A., Mazurenko I.L., Nikitin A.A. High-performance tone detection using a digital signal processor (DSP) having multiple arithmetic logic units (ALUs). United States Patent: 8,761,916, June 24, 2014. http://patft.uspto.gov/[...]
23. Parfenov D.V., Aliseychik P.A., Letunovskiy A.A., Markovic A., Mazurenko I.L., Parkhomenko D.V. Video transcoder with flexible quality and complexity management. United States Patent: 8,731,068, May 20, 2014. http://patft.uspto.gov/[...]
24. Aliseychik P.A., Letunovskiy A.A., Petyushko A. A., Parkhomenko D.V., Kholodenko A.B. Accelerator for a read-channel design and simulation tool. United States Patent: 8,713,495. April 29, 2014. http://patft.uspto.gov/[...]
25. Letunovskiy Aleksey, Parfenov Denis, Mazurenko Ivan, Markovic Alexander, Petyushko Alexander. Motion estimation for a video transcoder. United States Patent: 8,711,941, April 29, 2014. http://patft.uspto.gov/[...]
26. Panteleev P. A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Reconfigurable encoding per multiple communications standards. United States Patent: 8,700,969, April 15, 2014. http://patft.uspto.gov/[...]
27. Panteleev P. A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Branch metrics calculation for multiple communications standards. United States Patent: 8,699,396. April 15, 2014. http://patft.uspto.gov/[...]
28. Irmatov A.A., Buryak D.Yu., Kuznetsov V.D., Cherdakov D. V., Yang H.-K., Lee D.S. Method and apparatus for recognizing a protrusion on a face. United States Patent: 8,698,914, April 15, 2014. http://patft.uspto.gov/[...]
29. Gasanov E.E., Neznanov I.V., Shutkin Yu.S., Sokolov A.P., Panteleev P.A. Timer manager architecture based on binary heap. United States Patent: 8,656,206, February 18, 2014. https://patents.google.com/patent/US8656206B2/
30. Panteleev P.A., Gasanov E.E., Neznanov I.V., Sokolov A.P., Shutkin Yu.A. Reconfigurable BCH decoder. United States Patent: 8,621,329, December 31, 2013. http://patft.uspto.gov/[...]
31. Andreev A.E., Nikitin A.A., Scepanovic R., Vikhliantsev I.A. Method and apparatus for generating memory models and timing database. United States Patent: 8,566,769, October 22, 2013. http://patft.uspto.gov/[...]
32. Aliseychik P.A., Gasanov E.E., Izyumin O.N., Neznanov I.V., Panteleev P.A. Parallel true random number generator architecture. United States Patent: 8,539,009, September 17, 2013. http://patft.uspto.gov/[...]
33. Andreev A.E., Gasanov E.E., Aliseychik P.A., Neznanov I.V., Panteleev P.A. System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors. United States Patent: 8,527,851, September 3, 2013. http://patft.uspto.gov/[...]
34. Nikitin A.A, Scepanovic R., Kucherenko I.V., Lau W., Kong Cheng-Gang, Seto Hui-Yin, Zolotykh A.A., Pavisic I., Bhutani S., Lu A., Lyalin I.V.. Method and computer program for generating grounded shielding wires for signal wiring. United States Patent: 8,516,425, August 20, 2013. http://patft.uspto.gov/[...]
35. Mazurenko I.L., Aleshin S.V., Lyalin I.V., Nikitin A.A., Parfenov D.V. Adaptive filtering with flexible selection of algorithm complexity and performance. United States Patent: 8,515,055, August 20, 2013. http://patft.uspto.gov/[...]
36. Alekseev D.V., Galatenko A.V., Letunovskiy A.A., Markovic A., Nikitin A.A. Cryptographic processing using a processor. United States Patent: 8,452,006, May 28, 2013. http://patft.uspto.gov/[...]
37. Alekseev D.V., Galatenko A.V., Lyalin I.V., Markovic A., Parfenov D.V. Hash processing using a processor. United States Patent: 8,447,988, May 21, 2013. http://patft.uspto.gov/[...]
38. Andreev A.E., Gribok S.Y., Izyumin O. Variable node processing unit. United States Patent: 8,443,033, May 14, 2013. http://patft.uspto.gov/[...]
39. Irmatov A.A., Belousov A., Cadouri E., Gratchev A., Ryjov A.P., Thenie L. Method and mechanism for extraction and recognition of polygons in an IC design. United States Patent: 8,429,588, April 23, 2013. http://patft.uspto.gov/[...]
40. Neznanov I.V., Gasanov E.E., Panteleev P.A., Aliseychik P.A., Sokolov A.P. BCH or reed-solomon decoder with syndrome modification. United States Patent: 8,397,143, March 12, 2013. http://patft.uspto.gov/[...]
41. Gasanov E.E., Sokolov A.P., Panteleev P.A., Neznanov I.V., Aliseychik P.A. Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder. United States Patent: 8,365,054, January 29, 2013. http://patft.uspto.gov/[...]
42. Andreev A.E., Vukovic V., Vikhliantsev I.A. Circuits for implementing parity computation in a parallel architecture LDPC decoder. United States Patent: 8,347,167, January 1, 2013. http://patft.uspto.gov/[...]
43. Gashkov S.B., Andreev A.E. Universal Galois field multiplier. United States Patent: 8,312,072, November 13, 2012. http://patft.uspto.gov/[...]
44. Bolotov A.A., Grinchuk M.I., Ivanovic L.D., Galatenko A.V. Architecture and implementation method of programmable arithmetic controller for cryptographic applications. United States Patent: 8,302,083, October 30, 2012. http://patft.uspto.gov/[...]
45. Panteleev P.A., Gasanov E.E., Andreev A.E., Neznanov I.V., Aliseychik P.A. Scheme for erasure locator polynomial calculation in error-and-erasure decoder. United States Patent: 8,286,060, October 9, 2012. http://patft.uspto.gov/[...]
46. Gribok S.Y., Andreev A.E., Gashkov S.B. Cryptographic random number generator using finite field operations. United States Patent: 8,250,129, August 21, 2012. http://patft.uspto.gov/[...]
47. Andreev A.E., Nikitin А.A., Scepanovic R., Vikhliantsev I.A. Method and apparatus for generating memory models and timing database. United States Patent: 8,245,168, August 14, 2012. http://patft.uspto.gov/[...]
48. Nikitin Andrey, Scepanovic Ranko, Kucherenko Igor, Lau William, Kong Cheng-Gang, Seto Hui-Yin, Zolotykh Andrej, Pavisic Ivan, Bhutani Sandeep, Lu Aiguo, Lyalin Ilya. Method and apparatus for balancing signal delay skew. United States Patent: 8,239,813, August 7, 2012. http://patft.uspto.gov/[...]
49. Andreev A.E., Neznanov I.V., Gasanov E.E., Panteleev P.A. Reed-solomon decoder with a variable number of correctable errors. United States Patent: 8,209,589, June 26, 2012. http://patft.uspto.gov/[...]
50. Andreev A.E., Neznanov I.V., Gasanov E.E., Panteleev P.A. Configurable Reed-Solomon decoder based on modified Forney. United States Patent: 8,181,096, May 15, 2012. http://patft.uspto.gov/[...]
51. Panteleev P.A., Andreev A.E., Gasanov E.E., Neznanov I.V. Variable redundancy reed-solomon encoder. United States Patent: 8,176,397, May 8, 2012. http://patft.uspto.gov/[...]
52. Grinchuk M.I., Bolotov A.A., Ivanovic L.D., Zolotykh A.A., Galatenko A.V. Efficient implementation of arithmetical secure hash techniques. United States Patent: 8,160,242, April 17, 2012. http://patft.uspto.gov/[...]
53. Andreev A.E., Bolotov A.A., Grinchuk M.I. Data controlling in the MBIST chain architecture. United States Patent: 8,156,391, April 10, 2012. http://patft.uspto.gov/[...]
54. Andreev A.E., Vikhliantsev I.A. Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same. United States Patent: 8,151,160, April 3, 2012. http://patft.uspto.gov/[...]
55. Andreev A.E., Bolotov A.A., Scepanovic R. Memory mapping for parallel turbo decoding. United States Patent: 8,132,075, March 6, 2012. http://patft.uspto.gov/[...]
56. Andreev A.E., Gribok S.Y., Vukovic V. System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units. United States Patent: 8,095,845, January 10, 2012. http://patft.uspto.gov/[...]
57. Andreev A.E., Bolotov A.A., Grinchuk M.I. Transport subsystem for an MBIST chain architecture. United States Patent: 8,046,643. October 25, 2011. http://patft.uspto.gov/[...]
58. Andreev A.E., Nikitin А.A., Neznanov I.V., Scepanovic R. Method and apparatus for mapping design memories to integrated circuit layout. United States Patent: 8,037,432. October 11, 2011. http://patft.uspto.gov/[...]
59. Andreev A.E., Gribok S.Y., Izyumin O., Scepanovic R., Vikhliantsev I.A., Vukovic V. Methods and apparatus for programmable decoding of a plurality of code types. United States Patent: 8,035,537. October 11, 2011. http://patft.uspto.gov/[...]
60. Ирматов А.А., Буряк Д.Ю., Чердаков Д.В., Кузнецов В.Д., Янг Х.Е., Ли Д.С. Способ и устройство распознавания рельефности лица. Патент РФ ? 2431190, 10 октября, 2011. http://www.findpatent.ru/patent/243/2431190.html
61. Ирматов А.А., Буряк Д.Ю., Чердаков Д.В., Ли Д.С. Способ и устройство обнаружения лиц на изображении с применением каскада классификаторов. Патент РФ ? 2427911, 27 августа 2011. http://www.findpatent.ru/patent/242/2427911.html
62. Nikitin А.A., Andreev A.E., Scepanovic R. Method and system for outputting a sequence of commands and data described by a flowchart. United States Patent: 8,006,209, August 23, 2011. http://patft.uspto.gov/[...]
63. Andreev A.E., Bolotov A.A., Grinchuk M.I. Address controlling in the MBIST chain architecture. United States Patent: 7,949,909, May 24, 2011. http://patft.uspto.gov/[...]
64. Andreev A.E., Vikhliantsev I.A., Gribok S. Parallel LDPC decoder. United States Patent: 7,934,139, April 26, 2011. http://patft.uspto.gov/[...]
65. Gribok S., Andreev A.E., Vikhliantsev I.A. Low complexity LDPC encoding algorithm. United States Patent: 7,913,149, March 22, 2011. http://patft.uspto.gov/[...]
66. Irmatov A.A., Belousov A., Cadouri E., Gratchev A., Ryjov A.P., Thenie L. Method and mechanism for extraction and recognition of polygons in an IC design. United States Patent: 7,908,579, March 15, 2011. http://patft.uspto.gov/[...]
67. Andreev A.E., Bolotov A.A. Built in test controller with a downloadable testing program. United States Patent: 7,882,406, February 1, 2011. http://patft.uspto.gov/[...]
68. Andreev A.E., Vukovic V., Scepanovic R. Decision tree representation of a function. United States Patent: 7,877,724, January 25, 2011. http://patft.uspto.gov/[...]
69. Andreev A.E., Bolotov A.A., Scepanovic R. Command language for memory testing. United States Patent: 7,856,577, December 21, 2010. http://patft.uspto.gov/[...]
70. Ирматов А.А., Белоусов А., Кадоури Э., Грачев А., Рыжов А.П., Тени Л. Метод и механизм экстракции и распознавания многоугольников при проектировании интегральных схем. Патент РФ ? 2406136, 10 декабря, 2010. http://www.findpatent.ru/patent/240/2406136.html
71. Gasanov E.E., Andreev A.E., Neznanov I.V., Panteleev P.A., Gashkov S.B. Low area architecture in BCH decoder. United States Patent: 7,823,050, October 26, 2010. http://patft.uspto.gov/[...]
72. Nikitin А.A., Andreev A.E., Vikhliantsev I.A. Digital Gaussian noise simulator. United States Patent: 7,822,099, October 26, 2010. http://patft.uspto.gov/[...]
73. Andreev A.E., Pavisic I., Bolotov A.A. Density driven layout for RRAM configuration module. United States Patent: 7,818,703, October 19, 2010. http://patft.uspto.gov/[...]
74. Andreev A.E., Bolotov A.A., Scepanovic R. Generation of test sequences during memory built-in self testing of multiple memories. United States Patent: 7,788,563, August 31, 2010. http://patft.uspto.gov/[...]
75. Andreev A.E., Vukovic V., Scepanovic R. Pipelined LDPC arithmetic unit. United States Patent: 7,739,575, June 15, 2010. http://patft.uspto.gov/[...]
76. Andreev A.E., Vikhliantsev I.A., Scepanovic R. High performance tiling for RRAM memory. United States Patent: 7,739,471, June 15, 2010. http://patft.uspto.gov/[...]
77. Andreev A.E., Pavisic I., Vikhliantsev I.A. Methods and apparatus for fast unbalanced pipeline architecture. United States Patent: 7,667,494, February 23, 2010. http://patft.uspto.gov/[...]
78. Ирматов А.А., Кузнецов В.Д., Буряк Д.Ю., Чердаков Д.В., Ли Д.С., Мун В.Ж., Ли Я.Ж. Способ и система для обнаружения лица. Патент РФ ? 2382407, 20 февраля 2010. http://www.findpatent.ru/patent/238/2382407.html
79. Ирматов А.А., Буряк Д.Ю., Чердаков Д.В., Кузнецов В.Д., Мун В.Ж., Ли Я.Ж., Янг Х.Е., Ли Д.С. Способ и система для распознавания лица с учетом списка людей, не подлежащих проверке. Патент РФ ? 2381553, 10 февраля 2010. http://www.findpatent.ru/patent/238/2381553.html
80. Andreev A.E. Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data. United States Patent: 7,656,325, February 2, 2010. http://patft.uspto.gov/[...]
81. Andreev A.E., Nikitin А.A., Scepanovic R., Vikhliantsev I.A. Method and apparatus for generating memory models and timing database. United States Patent: 7,584,442, September 1, 2009. http://patft.uspto.gov/[...]
82. Zolotykh A.A., Gasanov E.E., Galatenko A.V., Lyalin I.V. Ramptime propagation on designs with cycles. United States Patent: 7,568,175, July 28, 2009. http://patft.uspto.gov/[...]
83. Andreev A.E., Bolotov A.A. Sequential tester for longest prefix search engines. United States Patent: 7,548,844, June 16, 2009. http://patft.uspto.gov/[...]
84. Gribok S.V., Andreev A.E., Pavisic I. Built in self test transport controller architecture. United States Patent: 7,546,505, June 9, 2009. http://patft.uspto.gov/[...]
85. Andreev A.E., Nikitin A.A., Scepanovic R. Multimode delay analysis for simplifying integrated circuit design timing models. United States Patent: 7,512,918, March 31, 2009. http://patft.uspto.gov/[...]
86. Lyalin I.V., Zolotykh A.A., Gasanov E.E., Galatenko A.V. Method of selecting cells in logic restructuring. United States Patent: 7,496,870, February 24, 2009. http://patft.uspto.gov/[...]
87. Rodin S.B., Aleshin S.V., Golubtsov I. Automatic recognition of geometric points in a target IC design for OPC mask quality calculation. United States Patent: 7,493,577, February 17, 2009. http://patft.uspto.gov/[...]
88. Andreev A.E., Vukovic V., Gribok S.V. RRAM memory error emulation. United States Patent: 7,493,519, February 17, 2009. http://patft.uspto.gov/[...]
89. Nikitin A.A., Andreev A.E., Scepanovic R. Method and system for outputting a sequence of commands and data described by a flowchart. United States Patent: 7,472,358, December 30, 2008. http://patft.uspto.gov/[...]
90. Andreev A.E., Gribok S.V., Bolotov A.A. Memory BISR architecture for a slice. United States Patent: 7,430,694, September 30, 2008. http://patft.uspto.gov/[...]
91. Andreev A.E., Nikitin A.A., Neznanov I.V., Scepanovic R. Method and apparatus for mapping design memories to integrated circuit layout. United States Patent: 7,424,687, September 9, 2008. http://patft.uspto.gov/[...]
92. Andreev A.E., Nikitin A.A., Scepanovic R. Method and system for outputting a sequence of commands and data described by a flowchart. United States Patent: 7,415,691, August 19, 2008. http://patft.uspto.gov/[...]
93. Andreev A.E., Bolotov A.A., Scepanovic R. Memory timing model with back-annotating. United States Patent: 7,415,686, August 19, 2008. http://patft.uspto.gov/[...]
94. Uzhakov S.V., Aleshin S.V., Medvedeva M.M. Method and system for improving aerial image simulation speeds. United States Patent: 7,406,675, July 29, 2008. http://patft.uspto.gov/[...]
95. Andreev A.E., Panteleev P.A., Nikitin A.A. Method and system for mapping netlist of integrated circuit to design. United States Patent: 7,404,166, July 22, 2008. http://patft.uspto.gov/[...]
96. Aleshin S.V., Medvedeva M.G., Rodin S.B., Egorov E.E. Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes. United States Patent: 7,401,318, July 15, 2008. http://patft.uspto.gov/[...]
97. Galatenko A.V., Gasanov E.E., Lyalin I.V. Method and apparatus for controlling congestion during integrated circuit design resynthesis. United States Patent: 7,401,313, July 15, 2008. http://patft.uspto.gov/[...]
98. Galatenko A.V., Gasanov E.E., Zolotykh A.A. Method and apparatus for performing logical transformations for global routing. United States Patent: 7,398,486, July 8, 2008. http://patft.uspto.gov/[...]
99. Panteleev P.A., Nikitin A.A., Andreev A.E. Method and system for converting netlist of integrated circuit between libraries. United States Patent: 7,380,223, May 27, 2008. http://patft.uspto.gov/[...]
100. Nikitin A.A., Neznanov I.V., Andreev A.E. RRAM controller built in self test memory. United States Patent: 7,356,743, April 8, 2008. http://patft.uspto.gov/[...]
101. Golubtsov I., Aleshin S.V., Scepanovic R., Rodin S.B., Medvedeva M.M., Uzhakov S.V., Egorov E.E., Strelkova N. Method and system for analyzing the quality of an OPC mask. United States Patent: 7,340,706, March 4, 2008. http://patft.uspto.gov/[...]
102. Nikitin A.A., Andreev A.E. Method for evaluating logic functions by logic circuits having optimized number of and/or switches. United States Patent: 7,328,423, February 5, 2008. http://patft.uspto.gov/[...]
103. Andreev A.E., Gribok S.V., Bolotov A.A. Memory BISR controller architecture. United States Patent: 7,328,382, February 5, 2008. http://patft.uspto.gov/[...]
104. Nikitin A.A., Andreev A.E., Scepanovic R. Verification of RRAM tiling netlist. United States Patent: 7,315,993, January 1, 2008. http://patft.uspto.gov/[...]
105. Andreev A.E., Vikhliantsev I.A., Vukovic V. Data stream frequency reduction and/or phase shift. United States Patent: 7,313,660, December 25, 2007. http://patft.uspto.gov/[...]
106. Andreev A.E., Gribok S., Bolotov A.A. Master controller architecture. United States Patent: 7,308,633, December 11, 2007. http://patft.uspto.gov/[...]
107. Andreev A.E., Scepanovic R. System and method for efficiently testing a large random access memory space. United States Patent: 7,305,597, December 4, 2007. http://patft.uspto.gov/[...]
108. Andreev A.E., Bolotov A.A., Scepanovic R. Memory mapping for parallel turbo decoding. United States Patent: 7,305,593, December 4, 2007. http://patft.uspto.gov/[...]
109. Andreev A.E., Gribok S., Bolotov A.A. RRAM communication system. United States Patent: 7,283,385, October 16, 2007. http://patft.uspto.gov/[...]
110. Nikitin A.A., Andreev A.E., Vikhliantsev I.A. Digital gaussian noise simulator. United States Patent: 7,263,470, August 28, 2007. http://patft.uspto.gov/[...]
111. Rodin S.B., Aleshin S.V., Medvedeva M.G. OPC edge correction based on a smoothed mask design. United States Patent: 7,260,814, August 21, 2007. http://patft.uspto.gov/[...]
112. Nikitin A.A., Andreev A.E. Method for optimizing execution time of parallel processor programs. United States Patent: 7,257,807, August 14, 2007. http://patft.uspto.gov/[...]
113. Galatenko A.V., Gasanov E.E., Zolotykh A.A., Lyalin I.V. Multiple buffer insertion in global routing. United States Patent: 7,257,791, August 14, 2007. http://patft.uspto.gov/[...]
114. Andreev A.E., Pavisic I., Bolotov A.A. Density driven layout for RRAM configuration module. United States Patent: 7,246,337, July 17, 2007. http://patft.uspto.gov/[...]
115. Zolotykh A.A., Gasanov E.E., Galatenko A.V., Lyalin I.V. Ramptime propagation on designs with cycles. United States Patent: 7,246,336, July 17, 2007. http://patft.uspto.gov/[...]
116. Andreev A.E., Bolotov A.A., Scepanovic R. Search engine for large-width data. United States Patent: 7,231,383, June 12, 2007. http://patft.uspto.gov/[...]
117. Nikitin A.A., Andreev A.E., Bolotov A.A. Process and apparatus for memory mapping. United States Patent: 7,219,321, May 15, 2007. http://patft.uspto.gov/[...]
118. Andreev A.E., Bolotov A.A., Scepanovic R. Method and BIST architecture for fast memory testing in platform-based integrated circuit. United States Patent: 7,216,278, May 8, 2007. http://patft.uspto.gov/[...]
119. Andreev A.E., Nikitin A.A., Vikhliantsev I.A. Process and apparatus for placing cells in an IC floorplan. United States Patent: 7,210,113, April 24, 2007. http://patft.uspto.gov/[...]
120. Andreev A.E., Vikhliantsev I.A., Pavisic I. Memory tiling architecture. United States Patent: 7,207,026, April 17, 2007. http://patft.uspto.gov/[...]
121. Andreev A.E., Nikitin A.A., Scepanovic R. RRAM memory timing learning tool. United States Patent: 7,200,826, April 3, 2007. http://patft.uspto.gov/[...]
122. Andreev A.E., Bolotov A.A. Sequential tester for longest prefix search engines. United States Patent: 7,200,785, April 3, 2007. http://patft.uspto.gov/[...]
123. Andreev A.E., Pavisic I., Bolotov A.A. Compact custom layout for RRAM column controller. United States Patent: 7,194,717, March 20, 2007. http://patft.uspto.gov/[...]
124. Andreev A.E., Gashkov S.B., Sedelev O.B., Nikitin A.A. RRAM flipflop rcell memory generator. United States Patent: 7,193,905, March 20, 2007. http://patft.uspto.gov/[...]
125. Andreev A.E., Bolotov A.A., Scepanovic R. FIFO memory with single port memory modules for allowing simultaneous read and write operations. United States Patent: 7,181,563, February 20, 2007. http://patft.uspto.gov/[...]
126. Andreev A.E., Nikitin A.A., Scepanovic R. Yield driven memory placement system. United States Patent: 7,168,052, January 23, 2007. http://patft.uspto.gov/[...]
127. Gashkov S.B., Andreev A.E. Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2. United States Patent: 7,167,886, January 23, 2007. http://patft.uspto.gov/[...]
128. Andreev A.E., Neznanov I.V., Nikitin A.A., Scepanovic R., Vikhliantsev I. Memory generation and placement. United States Patent: 7,155,688, December 26, 2006. http://patft.uspto.gov/[...]
129. Lyalin I.V., Zolotykh A.A., Gasanov E.E., Galatenko A.V. Method of selecting cells in logic restructuring. United States Patent: 7,146,591, December 5, 2006. http://patft.uspto.gov/[...]
130. Gasanov E.E., Lyalin I.V., Galatenko A.V., Zolotykh A.A. Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths. United States Patent: 7,111,267, September 19, 2006. http://patft.uspto.gov/[...]
131. Andreev A.E., Nikitin A.A., Scepanovic R. Process and apparatus for fast assignment of objects to a rectangle. United States Patent: 7,111,264, September 19, 2006. http://patft.uspto.gov/[...]
132. Nikitin A.A., Andreev A.E. Optimizing depths of circuits for Boolean functions. United States Patent: 7,103,868, September 5, 2006. http://patft.uspto.gov/[...]
133. Galatenko A.V., Kudryavtsev V.B., Gasanov E.E. Process and apparatus for placement of megacells in ICs design. United States Patent: 7,103,865, September 5, 2006. http://patft.uspto.gov/[...]
134. Andreev A.E., Scepanovic R., Vukovic V. Decomposer for parallel turbo decoding, process and integrated circuit. United States Patent: 7,096,413, August 22, 2006. http://patft.uspto.gov/[...]
135. Andreev A.E., Pavisic I., Ivanovic L. Method and system for classifying an integrated circuit for optical proximity correction. United States Patent: 7,093,228, August 15, 2006. http://patft.uspto.gov/[...]
136. Nikitin A.A., Andreev A.E. Method and apparatus of IC implementation based on C++ language description. United States Patent: 7,082,593, July 25, 2006. http://patft.uspto.gov/[...]
137. Andreev A.E., Bolotov A.A., Radovanovic N. Built-in functional tester for search engines. United States Patent: 7,082,561, July 25, 2006. http://patft.uspto.gov/[...]
138. Andreev A.E., Bolotov A.A., Vikhliantsev I.A. Integrated circuit and process for identifying minimum or maximum input value among plural inputs. United States Patent: 7,072,922, July 4, 2006. http://patft.uspto.gov/[...]
139. Andreev A.E., Vikhliantsev I.A., Scepanovic R. Controller architecture for memory mapping. United States Patent: 7,065,606, June 20, 2006. http://patft.uspto.gov/[...]
140. Andreev A.E., Vikhliantsev I.A., Bolotov A.A. Method for generating tech-library for logic function. United States Patent: 7,062,726, June 13, 2006. http://patft.uspto.gov/[...]
141. Andreev A.E., Vikhliantsev I.A., Scepanovic R. Pseudo-random one-to-one circuit synthesis. United States Patent: 7,050,582, May 23, 2006. http://patft.uspto.gov/[...]
142. Medvedeva M.G., Aleshin S.V., Egorov E.E., Rodin S.B. Gradient method of mask edge correction. United States Patent: 7,039,896, May 2, 2006. http://patft.uspto.gov/[...]
143. Nikitin A.A., Andreev A.E. Decision function generator for a Viterbi decoder. United States Patent: 7,039,855, May 2, 2006. http://patft.uspto.gov/[...]
144. Andreev A.E., Nikitin A.A., Vikhliantsev I.A. Process and apparatus for placement of cells in an IC during floorplan creation. United States Patent: 7,036,102, April 25, 2006. http://patft.uspto.gov/[...]
145. Andreev A.E., Scepanovic R. FFS search and edit pipeline separation. United States Patent: 7,035,844, April 25, 2006. http://patft.uspto.gov/[...]
146. Medvedeva M.G., Kalinin J.V., Aleshin S.V., Strelkova N. Quality measurement of an aerial image. United States Patent: 7,035,446, April 25, 2006. http://patft.uspto.gov/[...]
147. Andreev A.E., Scepanovic R., Pavisic I., Vukovic V. RRAM backend flow. United States Patent: 7,028,274, April 11, 2006. http://patft.uspto.gov/[...]
148. Gasanov E.E., Podkolzin A.S., Galatenko A.V. Method and apparatus for finding optimal unification substitution for formulas in technology library. United States Patent: 7,003,739, February 21, 2006. http://patft.uspto.gov/[...]
149. Andreev A.E., Scepanovic R. Table module compiler equivalent to ROM. United States Patent: 7,003,510, February 21, 2006. http://patft.uspto.gov/[...]
150. Aleshin S.V., Medvedeva M.G., Rodin S.B., Egorov E.E. Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes. United States Patent: 6,988,260, January 17, 2006. http://patft.uspto.gov/[...]
151. Andreev A.E., Scepanovic R. Universal gates for ICs and transformation of netlists for their implementation. United States Patent: 6,988,252, January 17, 2006. http://patft.uspto.gov/[...]
152. Andreev A.E., Vikhliantsev I.A., Pavisic I. Clock tree synthesis with skew for memory devices. United States Patent: 6,941,533, September 6, 2005. http://patft.uspto.gov/[...]
153. Andreev A.E., Vikhliantsev I.A., Ivanovic L.D. Built-in test for multiple memory circuits. United States Patent: 6,941,494, September 6, 2005. http://patft.uspto.gov/[...]
154. Andreev A.E., Scepanovic R. User selectable editing protocol for fast flexible search engine. United States Patent: 6,941,314, September 6, 2005. http://patft.uspto.gov/[...]
155. Gashkov S.B., Andreev A.E., Lu A. Optimization of adder based circuit architecture. United States Patent: 6,934,733, August 23, 2005. http://patft.uspto.gov/[...]
156. Aleshin S.V., Medvedeva M.G., Egorov E.E., Belokopytov G.V., Filseth P.G. Mask correction for photolithographic processes. United States Patent: 6,934,410, August 23, 2005. http://patft.uspto.gov/[...]
157. Aleshin S.V., Medvedeva M.G., Rodin S.B. Sidelobe correction for attenuated phase shift masks. United States Patent: 6,911,285, June 28, 2005. http://patft.uspto.gov/[...]
158. Nikitin A.A., Andreev A.E. Method for evaluating logic functions by logic circuits having optimized number of and/or switches. United States Patent: 6,901,573, May 31, 2005. http://patft.uspto.gov/[...]
159. Egorov E.E., Aleshin S.V., Scepanovic R. Method and system for constructing a hierarchy-driven chip covering for optical proximity correction. United States Patent: 6,898,780, May 24, 2005. http://patft.uspto.gov/[...]
160. Andreev E.A., Bolotov A.A., Scepanovic R., Andreev A.E. Memory that allows simultaneous read requests. United States Patent: 6,886,088, April 26, 2005. http://patft.uspto.gov/[...]
161. Gasanov E.E., Zolotykh A.A., Lu A. Method to find boolean function symmetries. United States Patent: 6,868,536, March 15, 2005. http://patft.uspto.gov/[...]
162. Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for optimizing the timing of integrated circuits. United States Patent: 6,868,535, March 15, 2005. http://patft.uspto.gov/[...]
163. Aleshin S.V., Medvedeva M.G., Kalinin J., Rodin S.B. First approximation for OPC significant speed-up. United States Patent: 6,854,104, February 8, 2005. http://patft.uspto.gov/[...]
164. Andreev A.E., Vikhliantsev; I.A. Netlist redundancy detection and global simplification. United States Patent: 6,848,094, January 25, 2005. http://patft.uspto.gov/[...]
165. Andreev A.E., Gasanov E.E., Scepanovic R. Multidirectional router. United States Patent: 6,845,495, January 18, 2005. http://patft.uspto.gov/[...]
166. Andreev A.E., Scepanovic R. Symbolic simulation driven netlist simplification. United States Patent: 6,842,750, January 11, 2005. http://patft.uspto.gov/[...]
167. Lu A., Pavisic I., Zolotykh A.A., Gasanov E.E. Process of restructuring logics in ICs for setup and hold time optimization. United States Patent: 6,810,515, October 26, 2004. http://patft.uspto.gov/[...]
168. Andreev A.E., Pavisic I., Scepanovic R. Process for layout of memory matrices in integrated circuits. United States Patent: 6,804,811, October 12, 2004. http://patft.uspto.gov/[...]
169. Andreev A.E., Scepanovic R. Method of decreasing instantaneous current without affecting timing. United States Patent: 6,795,954, September 21, 2004. http://patft.uspto.gov/[...]
170. Andreev A.E., Scepanovic R. Prefix comparator. United States Patent: 6,785,699, August 31, 2004. http://patft.uspto.gov/[...]
171. Andreev A.E., Pavisic I., Scepanovic R. Process layout of buffer modules in integrated circuits. United States Patent: 6,760,896, July 6, 2004. http://patft.uspto.gov/[...]
172. Andreev A.E., Ivanovic L., Pavisic I. Power routing with obstacles. United States Patent: 6,757,881, June 29, 2004. http://patft.uspto.gov/[...]
173. Andreev A.E., Scepanovic R. Editing protocol for flexible search engines. United States Patent: 6,735,600, May 11, 2004. http://patft.uspto.gov/[...]
174. Andreev A.E., Scepanovic R., Grinchuk M.I. Process for fast cell placement in integrated circuit design. United States Patent: 6,704,915, March 9, 2004. http://patft.uspto.gov/[...]
175. Nikitin A.A., Gasanov E.E., Zolotykh A.A. Overlap remover manager. United States Patent: 6,701,503, March 2, 2004. http://patft.uspto.gov/[...]
176. Gasanov E.E., Zolotykh A.A., Pavisic I., Lu A. Floor plan tester for integrated circuit design. United States Patent: 6,701,493, March 2, 2004. http://patft.uspto.gov/[...]
177. Gashkov S.B., Andreev A.E., Lu A. Optimization of comparator architecture. United States Patent: 6,691,283, February 10, 2004. http://patft.uspto.gov/[...]
178. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for dynamic buffer and inverter tree optimization. United States Patent: 6,681,373, January 20, 2004. http://patft.uspto.gov/[...]
179. Andreev A.E., Vukovic V. Spanning tree method for K-dimensional space. United States Patent: 6,665,850, December 16, 2003. http://patft.uspto.gov/[...]
180. Andreev A.E., Bolotov A.A., Scepanovic R. Fast free memory address controller. United States Patent: 6,662,287, December 9, 2003. http://patft.uspto.gov/[...]
181. Nikitin A.A., Zolotykh A.A., Radovanovic N. Direct transformation of engineering change orders to synthesized IC chip designs. United States Patent: 6,651,239, November 18, 2003. http://patft.uspto.gov/[...]
182. Gasanov E.E., Zolotykh A.A, Pavisic I., Lu A. Assignment of cell coordinates. United States Patent: 6,637,016, October 21, 2003. http://patft.uspto.gov/[...]
183. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for quick search for identities applicable to specified formula. United States Patent: 6,637,011, October 21, 2003. http://patft.uspto.gov/[...]
184. Gasanov E.E., Zolotykh A.A., Lu A., Pavisic I. Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells. United States Patent: 6,629,304, September 30, 2003. http://patft.uspto.gov/[...]
185. Gasanov E.E., Kudryavtsev V.B., Nikitin A.A. Blocked net buffer insertion. United States Patent: 6,615,401, September 2, 2003. http://patft.uspto.gov/[...]
186. Andreev A.E., Andreev E.A., Pavisic I. Optimal clock timing schedule for an integrated circuit. United States Patent: 6,615,397, September 2, 2003. http://patft.uspto.gov/[...]
187. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for formula area and delay minimization. United States Patent: 6,587,990, July 1, 2003. http://patft.uspto.gov/[...]
188. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for timing driven resynthesis. United States Patent: 6,564,361, May 13, 2003. http://patft.uspto.gov/[...]
189. Andreev A.E., Scepanovic R. Fast flexible search engine for longest prefix match. United States Patent: 6,564,211, May 13, 2003. http://patft.uspto.gov/[...]
190. Zolotykh A.A., Gasanov E.E., Pavisic I., Lu A. Timing recomputation. United States Patent: 6,553,551, April 22, 2003. http://patft.uspto.gov/[...]
191. Andreev A.E., Scepanovic R. Flexible search engine having sorted binary search tree for perfect match. United States Patent: 6,553,370, April 22, 2003. http://patft.uspto.gov/[...]
192. Lu A., Pavisic I., Zolotykh A.A., Gasanov E.E. Changing clock delays in an integrated circuit for skew optimization. United States Patent: 6,550,045, April 15, 2003. http://patft.uspto.gov/[...]
193. Pavisic I., Lu A., Zolotykh A.A., Gasanov E.E. Method in integrating clock tree synthesis and timing optimization for an integrated circuit design. United States Patent: 6,550,044, April 15, 2003. http://patft.uspto.gov/[...]
194. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for local resynthesis of logic trees with multiple cost functions. United States Patent: 6,543,032, April 1, 2003. http://patft.uspto.gov/[...]
195. Grinchuk M.I., Andreev A.E., Scepanovic R. Cell pin extensions for integrated circuits. United States Patent: 6,536,027, March 18, 2003. http://patft.uspto.gov/[...]
196. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for locating constants in combinational circuits. United States Patent: 6,536,016, March 18, 2003. http://patft.uspto.gov/[...]
197. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for optimal critical netlist area selection. United States Patent: 6,532,582, March 11, 2003. http://patft.uspto.gov/[...]
198. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for detecting equivalent and anti-equivalent pins. United States Patent: 6,530,063, March 4, 2003. http://patft.uspto.gov/[...]
199. Andreev A.E., Scepanovic R., Pavisic I. Chip core size estimation. United States Patent: 6,526,553, February 25, 2003. http://patft.uspto.gov/[...]
200. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for minimization of net delay by optimal buffer insertion. United States Patent: 6,519,746, February 11, 2003. http://patft.uspto.gov/[...]
201. Gasanov E.E., Zolotykh A.A., Postelga Yu.P. Density driven assignment of coordinates. United States Patent: 6,513,148, January 28, 2003. http://patft.uspto.gov/[...]
202. Andreev A.E., Bolotov A.A., Vikhliantsev I.A. Net delay optimization with ramptime violation removal. United States Patent: 6,507,939, January 14, 2003. http://patft.uspto.gov/[...]
203. Andreev A.E., Raspopovic P., Bolotov A.A. Channel router with buffer insertion. United States Patent: 6,505,336, January 7, 2003. http://patft.uspto.gov/[...]
204. Andreev A.E., Scepanovic R. Process, apparatus and program for transforming program language description of an IC to an RTL description. United States Patent: 6,487,698, November 26, 2002.
205. Lu A., Pavisic I., Zolotykh A.A. Distribution dependent clustering in buffer insertion of high fanout nets. United States Patent: 6,487,697, November 26, 2002.
206. Zolotykh A.A., Gasanov E.E., Pavisic I., Lu A. Parallelization of resynthesis. United States Patent: 6,470,487, October 22, 2002.
207. Andreev A.E., Scepanovic R., Ivanovic L. epsilon-discrepant self-test technique. United States Patent: 6,467,067, October 15, 2002.
208. Andreev A.E., Bolotov A.A., Raspopovic P. Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes. United States Patent: 6,453,453, September 17, 2002.
209. Andreev A.E., Pavisic I., Raspopovic P. Wire routing optimization. United States Patent: 6,412,102, June 25, 2002.
210. Rostoker M.D., Koford J.S., Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal architecture. United States Patent: 6,407,434, June 18, 2002.
211. Andreev A.E., Gasanov E.E., Scepanovic R., Raspopovic P. Method and apparatus for parallel simultaneous global and detail routing. United States Patent: 6,324,674, November 27, 2001.
212. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Programmable triangular shaped device having variable gain. United States Patent: 6,312,980, November 6, 2001.
213. Scepanovic R., Pavisic I., Koford J.S., Andreev A.E., Jones E. Advanced modular cell placement system. United States Patent: 6,292,929, September 18, 2001.
214. Pavisic I., Bolotov A.A., Andreev A.E., Scepanovic R. Modifying timing graph to avoid given set of paths. United States Patent: 6,292,924, September 18, 2001.
215. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for local optimization of the global routing. United States Patent: 6,289,495, September 11, 2001.
216. Aleshin S.V., Egorov E., Belokopitov G.V., Petranovic D. Geometric aerial image simulation. United States Patent: 6,263,299, July 17, 2001.
217. Raspopovic; P., Scepanovic R., Andreev A.E. Method and apparatus for coarse global routing. United States Patent: 6,260,183, July 10, 2001.
218. Gasanov E.E., Scepanovic R., Raspopovic P., Andreev A.E. Net routing using basis element decomposition. United States Patent: 6,253,363, June 26, 2001.
219. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for parallel Steiner tree routing. United States Patent: 6,247,167, June 12, 2001.
220. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for minimization of process defects while routing. United States Patent: 6,230,306, May 8, 2001.
221. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with overlap remover with minimal noise. United States Patent: 6,223,332, April 24, 2001.
222. Aleshin S.V., Belokopitov G.V., Scepanovic R. Mask having an arbitrary complex transmission function. United States Patent: 6,197,456, March 6, 2001.
223. Andreev A.E., Pavisic I., Scepanovic R. Method and apparatus for determining wire routing. United States Patent: 6,186,676, February 13, 2001.
224. Andreev A.E., Pavisic I., Raspopovic P. Metal layer assignment. United States Patent: 6,182,272, January 30, 2001.
225. Scepanovic R., Andreev A.E., Gasanov E.E., Raspopovic P. Method and apparatus for hierarchical global routing descend. United States Patent: 6,175,950, January 16, 2001.
226. Scepanovic R., Andreev A.E., Raspopovic P. Memory-saving method and apparatus for partitioning high fanout nets. United States Patent: 6,154,874, November 28, 2000.
227. Scepanovic R., Koford J.S., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints. United States Patent: 6,134,702, October 17, 2000.
228. Pavisic I., Scepanovic R., Andreev A.E. Method and apparatus for horizontal congestion removal. United States Patent: 6,123,736, September 26, 2000.
229. Petranovic D., Scepanovic R., Aleshin S.V., Grinchuk M.I., Gashkov S.B. Resynthesis method for significant delay reduction. United States Patent: 6,109,201, August 29, 2000.
230. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Triangular semiconductor or gate. United States Patent: 6,097,073, August 1, 2000.
231. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with sinusoidal optimization. United States Patent: 6,085,032, July 4, 2000.
232. Pavisic I., Scepanovic R., Andreev A.E. Method and apparatus for continuous column density optimization. United States Patent: 6,075,933, June 13, 2000.
233. Andreev A.E., Pavisic I., Scepanovic R. Method and apparatus for congestion driven placement. United States Patent: 6,070,108, May 30, 2000.
234. Scepanovic R., Andreev A.E., Pavisic I. Method and apparatus for congestion removal. United States Patent: 6,068,662, May 30, 2000.
235. Scepanovic R., Pavisic I., Koford J.S., Andreev A.E., Jones E. Advanced modular cell placement system. United States Patent: 6,067,409, May 23, 2000.
236. Scepanovic R., Andreev A.E., Pavisic I. Method and apparatus for vertical congestion removal. United States Patent: 6,058,254, May 2, 2000.
237. Scepanovic R., Koford J,S., Andreev A.E., Pavisic I. Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization. United States Patent: 6,038,385, March 14, 2000.
238. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with median control and increase in resolution. United States Patent: 6,030,110, February 29, 2000.
239. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with overlap remover with minimal noise. United States Patent: 6,026,223, February 15, 2000.
240. Scepanovic R., Andreev A.E., Pavisic I. Parallel processing of Integrated circuit pin arrival times. United States Patent: 6,000,038, December 7, 1999.
241. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Architecture having diamond shaped or parallelogram shaped cells. United States Patent: 5,973,376, October 26, 1999.
242. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with optimization of cell neighborhood system. United States Patent: 5,971,588, October 26, 1999.
243. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with functional sieve optimization technique. United States Patent: 5,963,455, October 5, 1999.
244. Scepanovic R., Jones E., Andreev A.E. Parallel processor implementation of net routing. United States Patent: 5,930,500, July 27, 1999.
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246. Scepanovic R., Koford J.S., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S., Roseboom E.M. Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles". United States Patent: 5,909,376, June 1, 1999.
247. Scepanovic R., Andreev A.E., Pavisic I. Integrated circuit floor plan optimization system. United States Patent: 5,898,597, April 27, 1999.
248. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with iterative one dimensional preplacement optimization. United States Patent: 5,892,688, April 6, 1999.
249. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Tri-directional interconnect architecture for SRAM. United States Patent: 5,889,329, March 30, 1999.
250. Scepanovic R., Andreev A.E., Pavisic I. Integrated circuit cell placement parallelization with minimal number of conflicts. United States Patent: 5,875,118, February 23, 1999.
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252. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal sense cell architecture. United States Patent: 5,872,380, February 16, 1999.
253. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with dispersion-driven levelizing system. United States Patent: 5,870,312, February 9, 1999.
254. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with fast procedure for finding a levelizing cut point. United States Patent: 5,870,311, February 9, 1999.
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256. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Triangular semiconductor NAND gate. United States Patent: 5,864,165, January 26, 1999.
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258. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with universal affinity driven discrete placement optimization. United States Patent: 5,844,811, December 1, 1998.
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260. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with minimizing maximal cut driven affinity system. United States Patent: 5,835,381, November 10, 1998.
261. Scepanovic R., Koford J.S., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S., Boyle D.B. Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip. United States Patent: 5,835,378, November 10, 1998.
262. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Triangular semiconductor "AND" gate device. United States Patent: 5,834,821, November 10, 1998.
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264. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. CAD for hexagonal architecture. United States Patent: 5,822,214, October 13, 1998.
265. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with neighborhood system driven optimization. United States Patent: 5,812,740, September 22, 1998.
266. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Transistors having dynamically adjustable characteristics. United States Patent: 5,811,863, September 22, 1998.
267. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with cell placement crystallization. United States Patent: 5,808,899, September 15, 1998.
268. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Polydirectional non-orthoginal three layer interconnect architecture. United States Patent: 5,808,330, September 15, 1998.
269. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal SRAM architecture. United States Patent: 5,801,422, September 1, 1998.
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271. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal architecture with triangular shaped cells. United States Patent: 5,789,770, August 4, 1998.
272. Scepanovic R., Koford J.S., Jones E.R., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and process for designing integrated circuit chips using generalized assignment. United States Patent: 5,784,287, July 21, 1998.
273. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal field programmable gate array architecture. United States Patent: 5,777,360, July 7, 1998.
274. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal DRAM array. United States Patent: 5,742,086, April 21, 1998.
275. Scepanovic R., Koford J.S., Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S., Roseboom E.M. Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization. United States Patent: 5,712,793, January 27, 1998.
276. Scepanovic R., Koford J.S., Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints. United States Patent: 5,699,265, December 16, 1997.
277. Scepanovic R., Koford J.S., Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters. United States Patent: 5,661,663, August 26, 1997.
278. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Microelectronic integrated circuit including triangular semiconductor "or" g. United States Patent: 5,654,563, August 5, 1997.
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280. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Microelectronic integrated circuit including triangular semiconductor "and" gate device. United States Patent 5,631,581, May 20, 1997.
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