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STL2 Server Board
Technical Product Specification

Intel Order Number A44368-002

Revision 1.1 December 27, 2000 Enterprise Platforms Group


Revision History

STL2 Server Board TPS

Revision History
Date 6/15/00 6/20/00 7/7/00 Revision Number 0.5 0.6 0.61 Modifications Initial release. Updated connector reference designators Updated silkscreen reference designators to agree with STL2 FAB2. Removed figure 2 -3, IB6566 IRQ routing diagram. Added BIOS recovery jumper information. Corrected grammar / spelling errors. Updated table 5 -1, STL2 Hardware Sensors, per recent information Updated Section 5: Jumpers and Connectors, per modifications to the STL2 Fab3 Silver boards. Updated Section 4.2: BIOS Setup, per modifications included in BIOS Release 1.1. Added power consumption information to Section 6. Released version Added estimated MTBF calculation for the STL2 and absolute maximum ratings to Section 6. Added note to Section 5.2.1.4 that i t is not necessary to s et the jumpers on the processor frequency jumper block 5E1 when using production level (SL Spec) processors. Modified step # 4 of Section 5.2.1.3 Performing a BIOS Recovery Boot.

8/24/00

0.7

9/22/00 12/27/00

1.0 1.1

Disclaimers
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design. The STL2 platform may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copyright © Intel Corporation 2000- 2001. *Other brands and names are the property of their respective owners.
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Table of Contents

Table of Contents
1. Introduction...................................................................................................................... 1-1 1.1 1.2 1.3 1.4 Purpose ......................................................................................................................... 1-1 Audience........................................................................................................................ 1-1 STL2 Server Board Feature Overview....................................................................... 1-1 STL2 Server Board Block Diagram ........................................................................... 1-2

2. STL2 Server Board Architecture Overview.............................................................. 2-3 2.1 Intel® Pentium® III Processor Subsystem.................................................................. 2-3 Supported Processor Types ................................................................................. 2-3 Dual Processor Operation..................................................................................... 2-4 PGA370 Socket ..................................................................................................... 2-4 Processor Bus Termination / Regulation / Power ............................................... 2-4 Termination Package............................................................................................. 2-4 APIC Bus ................................................................................................................. 2-4 Boxed Processors.................................................................................................. 2-4

2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.2 2.3 2.4

ServerWorks ServerSet III LE Chipset ....................................................................... 2-5 Memory .......................................................................................................................... 2-5 PCI I/O Subsystem........................................................................................................ 2-6 64-bit / 66 MHz PCI Subsystem ............................................................................ 2-6 32-bit/33 MHz PCI Subsystem .............................................................................. 2-8

2.4.1 2.4.2 2.5

Chipset Support Components...................................................................................2-13 Legacy I/O (Super I/O) National* PC97317VUL ...............................................2-13 BIOS Flash ............................................................................................................2-15

2.5.1 2.5.2

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2.5.3 2.6

External Device Connectors................................................................................2-15

Interrupt Routing ..........................................................................................................2-15 Default I/O APIC ....................................................................................................2-15 Extended I/O APIC ...............................................................................................2-15 PCI Ids ...................................................................................................................2-18 Relationship between PCI IRQ and PCI Device ...............................................2-18

2.6.1 2.6.2 2.6.3 2.6.4

3. Server Management..................................................................................................... 3-21 3.1 3.2 3.3 3.4 3.5 Baseboard Management Controller .........................................................................3-21 Hardware Sensors......................................................................................................3-22 ACPI.............................................................................................................................3-26 AC Link Mode .............................................................................................................3-26 Wake On LAN Function .............................................................................................3-27

4. Basic Input Output System (BIOS)........................................................................... 4-29 4.1 BIOS Overview............................................................................................................4-29 System BIOS .........................................................................................................4-30 Flash Update Utility ..............................................................................................4-30

4.1.1 4.1.2 4.2

Setup Utility..................................................................................................................4-31 Configuration Utilities Overview..........................................................................4-31 Setup Utility Operation .........................................................................................4-31

4.2.1 4.2.2 4.3 4.4 4.5

CMOS Memory Definition..........................................................................................4-43 CMOS Default Override .............................................................................................4-43 Flash Update Utility.....................................................................................................4-43 Loading the System BIOS ...................................................................................4-44 OEM Customization .............................................................................................4-44 Language Area .....................................................................................................4-48
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4.5.4 4.6

Recovery Mode.....................................................................................................4-48

Error Messages and Error Codes ............................................................................4-48 POST Codes ........................................................................................................4-48 POST Error Codes and Messages ....................................................................4-53

4.6.1 4.6.2 4.7

Identifying BIOS and BMC Revision Levels .............................................................4-56 BIOS Revision Level Identification......................................................................4-56 BMC Revision Level Identification......................................................................4-56

4.7.1 4.7.2 4.8

Adaptec SCSI Utility...................................................................................................4-56 Running the SCSI Utility .......................................................................................4-57 Adaptec SCSI Utility Configuration Settings .....................................................4-57 Exiting Adaptec SCSI Utility................................................................................4-59

4.8.1 4.8.2 4.8.3

5. Jumpers and Connectors .......................................................................................... 5-61 5.1 5.2 STL2 Server Board Jumper and Connector Locations ..........................................5-61 Jumper Blocks ............................................................................................................5-63 Setting CMOS/Password Clear Jumper Block 1J15 .......................................5-63 Setting Configuration Jumper Block 1L4 ...........................................................5-67 Setting Configuration Jumper Block 6A.............................................................5-67

5.2.1 5.2.2 5.2.3 5.3

Connectors ..................................................................................................................5-67 Main ATX Power Connector (P33).....................................................................5-68 Auxilary ATX Power Connector (P34)................................................................5-68 I2C Power Connector (P37).................................................................................5-68 System Fan Connectors (P29, P27, P11) .........................................................5-69 Processor Connectors (P12, P36) .....................................................................5-69 Speaker Connector (P31) ...................................................................................5-69 Speaker Connector (P25) ...................................................................................5-69
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5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7
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5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20

Diskette Drive Connector (P20) .........................................................................5-70 SVGA Video Port .................................................................................................5-70 Keyboard and Mouse Connectors ...................................................................5-71 Parallel Port ........................................................................................................5-71 Serial Ports COM1 and COM2.........................................................................5-72 RJ-45 LAN Connector .......................................................................................5-72 USB Connectors ................................................................................................5-72 Ultra SCSI Connector (P9) ................................................................................5-73 Ultra160 SCSI Connector (P8) .........................................................................5-73 IDE Connector (P19) .........................................................................................5-74 32-Bit PCI Connector.........................................................................................5-75 64-Bit PCI Connector.........................................................................................5-76 Front Panel 24-pin Connector Pinout (P23) ....................................................5-77

6. Baseboard Specifications .......................................................................................... 6-81 6.1 6.2 6.3 6.4 6.5 Estimated Baseboard MTBF ....................................................................................6-81 Absolute Maximum Ratings .......................................................................................6-82 Calculated Power Consumption ...............................................................................6-82 Measured Power Consumption ................................................................................6-83 Mechanical Specifications .........................................................................................6-84

7. Regulatory and Integration Information ................................................................. 7-87 7.1 7.2 Regulatory Compliance..............................................................................................7-87 Installation Instructions ................................................................................................7-88 Ensure EMC ..........................................................................................................7-88 Ensure Host Computer and Accessory Module Certifications ........................7-89 Prevent Power Supply Overload .........................................................................7-89
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7.2.4 7.2.5 7.2.6

Place Battery Marking on Computer ..................................................................7-89 Use Only for Intended Applications .....................................................................7-90 Installation Precautions ........................................................................................7-90

8. Errata Listing ................................................................................................................. 8-91 8.1 Summary Errata Table ...............................................................................................8-91 Codes Used in Summary Table ..........................................................................8-91

8.1.1 8.2

Errata ...........................................................................................................................8-91

Appendix A: Glossary ............................................................................................................... i Appendix B: Reference Documents ................................................................................... III

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List of Figures
Figure 1 -1. STL2 Server Board Block Diagram ..................................................................... 1-2 Figure 2 -1. Embedded NIC PCI Signa ls ................................................................................. 2-9 Figure 2 -2. Video Controller PCI Signals ..............................................................................2-10 Figure 2 -3. STL2 Baseboard Interrupt Routing Diagram (PIC mode) ...............................2-16 Figure 2 -4. STL2 Baseboard Interrupt Routing Diagram (Symmetric mode) ...................2-17 Figure 5 -1. STL2 Server Board Jumper and Connector Locations ...................................5-61 Figure 5 -2. I/O Back Panel Connectors .................................................................................5-62 Figure 5 -3. STL2 Jumper Locations ......................................................................................5-63 Figure 5 -4. Diskette Drive Connector Pin Diagram .............................................................5-70 Figure 5 -5. IDE Connector Pin Diagram ...............................................................................5-74

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List of Tables
Table 2 -1. STL2 Server Board Supported Processors ......................................................... 2-3 Table 2 -2. SCSI Transfer Speeds ............................................................................................ 2-7 Table 2 -3. Embedded SCSI Supported PCI Commands ..................................................... 2-7 Table 2 -4. Video Controller Supported PCI C ommands .....................................................2-11 Table 2 -5. Standard VGA Modes...........................................................................................2-11 Table 2 -6. STL2 PCI IDs .........................................................................................................2-18 Table 2 -7. STL2 Relationship between PCI IRQ and PCI Device ......................................2-18 Table 3 -1. STL2 Hardware Sensors ......................................................................................3-22 Table 3 -2. STL2 Supported System Event Log (SEL) events ............................................3-23 Table 4 -1. Setup Utility Screen ...............................................................................................4-31 Table 4 -2. Main Menu Selections ...........................................................................................4-34 Table 4 -3. Primary Master and Slave Adapters Submenu Selections ...............................4-35 Table 4 -4. Processor Settings Submenu Selections ...........................................................4-35 Table 4 -5. Advanced Menu Selections ..................................................................................4-36 Table 4 -6. Memory Reconfiruation Submenu Selections ....................................................4-36 Table 4 -7. Peripheral Configuration Submenu Selections ..................................................4-37 Table 4 -8. PCI Device Submenu Selections.........................................................................4-38 Table 4 -9. Option ROM Submenu Selections .......................................................................4-38 Table 4 -10. Numlock Submenu Selections ...........................................................................4-39 Table 4 -11. Security Menu Selections ...................................................................................4-39 Table 4 -12. Secure Mode Submenu Selections ...................................................................4-40 Table 4 -13. Server Menu Selections ......................................................................................4-40 Table 4 -14. Wake On Events Submenu Selections .............................................................4-41 Table 4 -15. Console Redirection Submenu Selections .......................................................4-41 Table 4 -16. Boot Menu Selections .........................................................................................4-41 Table 4 -17. Boot Device Priority Selections .........................................................................4-42 Table 4 -18. Hard Drive Selections .........................................................................................4-42 Table 4 -19. Removable Devices Selections .........................................................................4-42 Table 4 -20. Exit Menu Selections ...........................................................................................4-43
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List of Tables

Table 4 -21. User Binary Area Scan Point Definitions ..........................................................4-47 Table 4 -22. Format of the User Binary Information Structure ..............................................4-47 Table 4 -23. Port-80h Code Definition....................................................................................4-49 Table 4 -24. Standard BIOS Port-80 Codes ..........................................................................4-49 Table 4 -25. Recovery BIOS Port-80 Codes..........................................................................4-52 Table 4 -26. POST Error Messages and Codes ...................................................................4-53 Table 4 -27. POST Error Conditions and Beep Codes ........................................................4-55 Table 4 -28. Channel Configuration ........................................................................................4-57 Table 4 -29. Adapter Selection Options .................................................................................4-57 Table 4 -30. Active Keys for SCSI Utility Screens .................................................................4-57 Table 4 -31. Adaptec SCSI Utility Setup Configurations ......................................................4-58 Table 5 -1. Jumper Block 1J15 Settings ................................................................................5-64 Table 5 -2. Jumper Block 5E1 Settings ..................................................................................5-66 Table 5 -3. Jumper Block 1J15 Default Settings ...................................................................5-66 Table 5 -4. Jumper Block 1L4 Settings ..................................................................................5-67 Table 5 -5. Jumper Block 6A Settings ....................................................................................5-67 Table 5 -6. Main ATX Power Connector Pinout.....................................................................5-68 Table 5 -7. Auxiliary ATX Power Connector P inout...............................................................5-68 Table 5 -8. I2C Power Connector Pinout.................................................................................5-68 Table 5 -9. Board Fan Connector Pinout................................................................................5-69 Table 5 -10. Processor Fan Connector Pinout ......................................................................5-69 Table 5 -11. Speaker Connector Pinout .................................................................................5-69 Table 5 -12. Speaker Connector Pinout .................................................................................5-69 Table 5 -13. Diskette Drive Connector Pinout .......................................................................5-70 Table 5 -14. Video Port C onnector Pinout .............................................................................5-70 Table 5 -15. Keyboard and Mouse Connector Pinouts.........................................................5-71 Table 5 -16. Parallel Port Connector Pinouts.........................................................................5-71 Table 5 -17. Serial Ports COM1 and COM2 Connector Pinouts .........................................5-72 Table 5 -18. RJ -45 LAN Connector Signals ...........................................................................5-72 Table 5 -19. USB Connectors..................................................................................................5-72 Table 5 -20. Ultra SCSI Connector Pinout..............................................................................5-73 Table 5 -21. Ultra160 SCSI Connector ...................................................................................5-73
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Table 5 -22. IDE Connector Pinout .........................................................................................5-74 Table 5 -23. 32-Bit PCI Connector Pinout ..............................................................................5-75 Table 5 -24. 64-Bit PCI Connctor Pino ut ................................................................................5-76 Table 5 -25. Front Panel 24-pin Connector Pinout ................................................................5-77 Table 6 -1. Estimated MTBF Calculated Numbers for STL2 ...............................................6-81 Table 6 -2. Absolute Maximum Ratings ..................................................................................6-82 Table 6 -3. STL2 Server Board Calculated Power Consumption........................................6-82 Table 6 -4. STL2 Server Board Measured Power Consumption.........................................6-83 Table 7 -1. Safety Regulations .................................................................................................7-87 Table 7 -2. EMC Regulations ...................................................................................................7-87

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Introduction

1.
1.1

Introduction
Purpose

This document provides an architectural overview of the STL2 s erver board, including the board layout of major components and connectors, and an overview of the server board's feature set.

1.2

Audience

This document is written for technical personnel who want a technical overview of the STL2 server board. Familiarity with the personal computer, Intel server architecture and the Peripheral Component Interconnect (PCI) local bus architecture is assumed.

1.3
·

STL2 Server Board Feature Overview
Dual Intel® Pentium® III processor support - Support for one or two identical Intel Pentium III processors for the PGA370 socket, which utilizes a new package technology called the Flip Chip Pin Grid Array (FCPGA) package - One embedded Voltage Regulating Module (VRM) for support of the primary processor, and one VRM connector for support of the secondary processor ServerWorks* ServerSet* III LE chipset - 133-MHz Front Side Bus (FSB) Capability - NB6635 North Bridge 3.0 LE - IB6566 South Bridge Support for four 3.3-V, registered ECC SDRAM DIMMs that are compliant with the JEDEC PC133 specification - Support for DIMM sizes 64 MB to 1 GB. Four DIMM slots allow a maxiumum installed memory of 4 GBs - ECC single-bit correction, and multiple-bit detection 64-bit, 66-MHz, 3.3-V keyed PCI segment with two expansion connectors and one embedded device - Two 64-bit, 66-MHz, 3.3-V keyed PCI expansion slots - Integrated on-board Adaptec * AIC7899 PCI dual-port SCSI controller that provides separate Ultra160 and Ultra Wide SCSI channels 32-bit, 33-MHz, 5-V keyed PCI segment with four expansion connectors and three embedded devices - Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots - IB6566 South Bridge, which provides Integrated Device Electronics (IDE) and Universal Serial Bus (USB) controller functions

The STL2 server board provides the following features:

·

·

·

·

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·

Integrated on-board Intel® EtherExpressTM PRO100+ 10/100megabit PCI Ethernet controller (Intel® 82559) with an RJ-45 Ethernet connector Integrated on-board ATI Rage* IIC video controller with 4 MB of on-board SGRAM video memory

Compatibility bus segment with three embedded devices - Super I/O Controller (PC97317) that provides all PC-compatible I/O (floppy, parallel, serial, keyboard, mouse, and Real-Time Clock) - Baseboard Management Controller (BMC ) (DS80CH11) that provides monitoring, alerting, and logging of critical system information including thermal, voltage, fan, and chassis intrusion information obtained from embedded sensors on the server board - 8-MB Flash device for system BIOS Dual Universal Serial Bus (USB) ports One IDE connector Flash BIOS support for all of the above Extended ATX board form factor (12" x 13")

· · · ·

1.4

STL2 Server Board Block Diagram

The STL2 server board offers a "flat" design, with the processors and memory subsystems residing on the board. The following figure shows the major functional blocks of the STL2 server board. The following section describes the major components of the server board.

STL2 Server Board Block Diagram

133 MHz System Bus
Two 64-bit/66-MHz, 3.3-V PCI
S2 S3

PCI 64-bit/66-MHz

SCSI Adaptec* AIC7899

NB6635 North Bridge 3.0 LE

PC133 Registered ECC SDRAM DIMMs

Two 32-bit/33-MHz, 5 -V PCI
S6 S5 S4 S1

PCI 32-bit/33-MHz

IB6566 South Bridge
ISA Bus BIOS FLASH

Two USB IDE

ServerSet* 3.0 LE STL2 Features
Floppy Keyboard, Mouse Two Serial Ports Parallel Port

10/100 LAN Intel 82559

PCI Video ATI* Rage IIC
SGRAM 4 MB

BMC
80CH11

Super I/O
PC97317VUL RTC

Figure 1-1. STL2 Server Board Block Diagram

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STL2 Server Board Architecture Overview

2.

STL2 Server Board Architecture Overview

The architecture of the STL2 server board is based on a design that supports dual-processor operation with Intel Pentium III processors and the ServerWorks ServerSet III LE chipset. The STL2 server contains embedded devices for video, Network Interface Card (NIC), SCSI, and IDE. The STL2 server board also provides support for server management and monitoring hardware, and interrupt control that supports dual-processor and PC/AT compatible operation. The section provides an overview of the following STL2 subsystems:
· · · · · ·

Pentium III processor subsystem SeverWorks ServerSet III LE chipset Memory PCI subsystem Chipset support components BMC server management controller

2.1

Intel® Pentium® III Processor Subsystem

The STL2 server board is designed to accommodate one or two Intel Pentium III processors for the PGA370 socket. The Pentium III processor for the PGA370 socket is the next member of the P6 family in the Intel IA-32 processor line. This processor uses the same core and offers the s ame performance as the Intel Pentium III processor for the SC242 connector, but utilizes a FCPGA. This package utilizes the same 370-pin zero-insertion force socket (PGA370) used by the Intel® CeleronTM processor. The STL2 server board utilizes Pentium III PGA370 socket processors, which interface with the front side bus at 133 MHz.

2.1.1

Supported Processor Types

The table below summarizes the processors that are planned to be supported on the STL2 server board:
Table 2-1. STL2 Server Board Supported Processors
Speed 1 GHz 933 MHz 866 MHz 800 MHz 733 MHz 667 MHz FSB Frequency 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz Cache Size 256 K 256 K 256 K 256 K 256 K 256 K

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2.1.2

Dual Processor Operation

The Pentium III processor interface is designed to be multi-processor (MP)-ready. Each processor contains a local Intel Advanced Programmable Interrupt Controller (APIC) section for interrupt handling. When two processors are installed, both processors must be of identical revision, core voltage, and bus/core speeds.

2.1.3

PGA370 Socket

The STL2 server board provides two PGA370 sockets. These are 370-pin zero-insertion force (ZIF) sockets that a FC-PGA package technology processor plugs into.

2.1.4

Processor Bus Termination / Regulation / Power

The termination circuitry required by the Intel Pentium III processor bus (AGTL+) signaling environment, and the circuitry to set the AGTL+ reference voltage, are implemented directly on the processor. The STL2 server board provides VRM 8.4 compliant DC-to-DC converters to provide processor power ,Voltage Controlled Current Plane (VCCP), at each PGA370 socket. The server board provides an embedded VRM for the primary processor and a VRM socket for the secondary processor. These are powered from the +5-V supply.

2.1.5

Termination Package

If a processor is not installed in a PGA370 socket, a termination package must be installed in the vacant socket to ensure reliable termination.

2.1.6

APIC Bus

Interrupt notification and generation for the processors is done using an independent path between local APICs in each processor and the I/O APIC located in the IB6566 South Bridge component.

2.1.7

Boxed Processors

The Intel Pentium III processor for the PGA370 socket is offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from a server board and standard components. 2.1.7.1 Boxed Process Fan Heatsinks

The boxed Pentium III processor for the PGA370 socket will be supplied with an unattached fan heatsink that has an integrated clip. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. Note that the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. The boxed processor thermal solution must be installed by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370-pin ZIF socket. The boxed processor's fan heatsink requires a +12-V power supply. A fan power cable is attached to the fan and connects to processor fan headers on the STL2 server board.

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The boxed processor fan heatsink will keep the processor core at the recommended junction temperature, as long as airflow through the fan heatsink is unimpeded. It is recommended that the air temperature entering the fan inlet be below 45 °C (measured at 0.3 inches above the fan hub).

2.2

ServerWorks ServerSet III LE Chipset

The ServerWorks ServerSet III LE chipset provides an integrated I/O bridge and memory controller and a flexible I/O subsystem core (PCI), targeted for multiprocessor systems and standard high-volume servers that are based on the Intel Pentium III processor. The ServerWorks ServerSet III LE chipset consists of two components:
·

NB6635 North Bridge 3.0 LE The NB6635 North Bridge 3.0 LE is responsible for accepting access requests from the host (processor) bus and for directing those accesses to memory or to one of the PCI buses. The NB6635 North Bridge 3.0 LE monitors the host bus, examining addresses for each request. Accesses may be directed to a memory request queue for subsequent forwarding to the memory subsystem, or to an outbound request queue for subsequent forwarding to one of the PCI buses. The NB6635 North Bridge 3.0 LE is reponsible for controlling data transfers to and from the memory. The NB6635 North Bridge 3.0 LE provides the interface for both the 64-bit/66-MHz, Revision 2.2-compliant PCI bus and the 32-bit/33-MHz, Revision 2.2-compliant PCI bus. The NB6635 North Bridge 3.0 LE is both a master and target on both PCI buses. IB6566 South Bridge The IB6566 South Bridge controller has several components. It can be both a master and a target on the 32-bit/33-MHz PCI bus. The IB6566 South Bridge also includes a USB controller and an IDE controller. The IB6566 South Bridge is responsible for many of the power management functions, with Advanced Configuration and Power Interface (ACPI) control registers built in. The IB6566 South Bridge provides a number of Infiniband pins.

·

2.3

Memory

The STL2 server board contains four 168-pin DIMM sockets. Memory is partitioned as four banks of registered SDRAM DIMMs, each of which provides 72 bits of noninterleaved memory (64-bit main memory plus ECC). The STL2 server board supports up to four 3.3-V, registered ECC SDRAM DIMMs that are compliant with the JEDEC PC133 specification. A wide range of DIMM sizes are supported, including 64 MB, 128 MB, 256 MB, 512 MB, and 1-GB DIMMs. The minimum supported memory configuration is 64 MB using one DIMM. The maximum configurable memory size is 4 GB using four DIMMs.

Note: Neither PC100 DIMMs nor non-ECC DIMMs can be used.
DIMMs may be installed in one, two, three, or four DIMM slots and must be populated starting with the lowest numbered slot and filling the slots in consecutive order. Empty memory slots between DIMMs are not supported. Although the STL2 server board architecture allows the user to mix various sizes of DIMMS, Intel recommends that module and DRAM vendors not be mixed in the same server system.
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System memory begins at address 0 and is continuous (flat addressing) up to the maximum amount of DRAM installed (exception: system memory is noncontiguous in the ranges defined as memory holes using configuration registers). The server board supports both base (conventional) and extended memory.

2.4

PCI I/O Subsystem

The expansion capabilities of the STL2 server board meet the needs of file and application servers for high performance I/O by providing two PCI bus segments in the form of one 64-bit / 66-MHz bus segment and one 32-bit / 33-MHz bus segment. Each of the PCI buses comply with Revision 2.2 of the PCI Local Bus Specification.

2.4.1

64-bit / 66 MHz PCI Subsystem

The 64-bit, 66-MHz, 3.3-V keyed PCI segment includes the following embedded devices and connectors:
· ·

Two 64-bit, 66-MHz, 3.3-V keyed PCI expansion slots that can support 66-MHz, 64/32-bit cards or 33-MHz, 64/32-bit cards. Integrated Adaptec AIC-7899 PCI dual-port SCSI controller providing separate Ultra160 and Ultra Wide SCSI channels

64-bit PCI features include:
· · · · · ·

Bus speed up to 66 MHz 3.3-V signaling environment Burst transfers up to a peak of 528 Megabytes per second (MBps) 8-, 16-, 32-, or 64-bit data transfers Plug-and-Play ready Parity enabled

Note: If a 33-MHz PCI board is installed into one of the 64-bit PCI slots, the bus speed for the 66MHz PCI slots and SCSI controller is decreased to 33-MHz. 2.4.1.1 Ultra160 / Ultra WideSCSI Controller

The STL2 server board includes an Adaptec AIC7899. This is an embedded dual-function, PCI SCSI host adapter on the 64-bit/66-MHz PCI bus. The AIC7899 contains two independent SCSI controllers that share a single PCI bus master interface as a multi-function device. Internally, each controller is identical, capable of operations using either 16-bit Single Ended (SE) or Low Voltage Differential (LVD) SCSI providing 40 MBps (Ultra-wide SE) or 160 MBps (Ultra160). The STL2 server board provides the ability to disable the embedded Ultra160 SCSI controller in the BIOS Setup option. When disabled, it will not be visible to the operating system.

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Table 2-2. SCSI Transfer Speeds
SCSI Port SE LVD Asynchronous Yes Yes Fast-5 yes yes Fast-10 yes yes Fast-20 yes yes Fast-40 no yes Fast-80/Ultra160 no yes

In the STL2 server board implementation, channel A provides a 68-pin, 16-bit LVD interface. Channel B provides a 68-pin, 16-bit SE Ultra Wide SCSI interface. Each its own set of PCI configuration registers and SCSI I/O registers. As a PCI 2.1/2.2 the AIC-7899 supports burst data transfers on PCI up to the maximum rate of 133 on-chip buffers.

Ultra160 SCSI controller has bus master, MBps using

Refer to the AIC-7899 PCI-Dual Channel SCSI Multi-Function Controller Data Manual for more information on the internal operation of this device and for descriptions of SCSI I/O registers. 2.4.1.1.1 AIC-7899 Supported PCI Commands

The AIC-7899 supports PCI commands as shown in the following table:
Table 2-3. Embedded SCSI Supported PCI Commands
AIC-7899 Support Target Master No No
2 2

C/BE [3::0] _L 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Notes: 1. 2. 3. 4. 5. 6.

Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate

No No

1 1

Yes Yes No No
1 1

No No No No

Yes Yes No
1

2, 3 2

Yes Yes No No No No

4 4

No1 Yes Yes Yes Yes Yes Yes
5 6 5 7

Yes Yes Yes Yes

4

4

Ignored after checking address parity. Support for 8 -bit transfers only for all registers in its device register space. Support for 32-bit transfers only for the external ROM/ EEPROM. Support for transfers from system memory. Defaults to Memory Read. Will respond to DAC if PCI Address matches the MBAR[63:12].

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7.

Defaults to Memory Write.

The extensions to memory commands (memory read multiple, memory read line, and memory write and invalidate) work with the cache line size register to give the cache controller advance knowledge of the minimum amount of data to expect. The decision to use either the memory read line or memory read multiple commands is determined by a bit in the configuration space command register for this device. 2.4.1.1.2 SCSI Bus

The SCSI data bus is 8 or 16 bits wide with odd parity generated per byte. SCSI control signals are the same for either bus width. To accommodate 8-bit devices on the 16-bit wide SCSI connector, the AIC-7899 assigns the highest arbitration priority to the low byte of the 16-bit word. This way, 16-bit targets can be mixed with 8-bit if the 8-bit devices are placed on the low data byte. For 8-bit mode, the unused high data byte is s elf-terminated and does not need to be connected. During chip power-down, all inputs are disabled to reduce power consumption.

2.4.2
· · · ·

32-bit/33 MHz PCI Subsystem
Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots Integrated Intel® EtherExpressTM PRO100+ 10/100 megabit PCI Ethernet controller (Intel® 82559) Integrated ATI Rage* IIC video controller with 4 MB of on-board SGRAM IB6566 South Bridge I/O APIC, PCI-to- Industry Standard Architecture (ISA) bridge, IDE controller, USB controller, and power management.

The 32-bit, 33-MHz, 5-V keyed PCI includes the following embedded devices and connectors:

32-bit PCI features include:
· · · · · ·

Bus speed up to 33 MHz 5-V signaling environment Burst transfers up to a peak of 132 MBps 8-, 16-, or 32-bit data transfers Plug-and-Play ready Parity enabled Network Interface Controller (NIC)

2.4.2.1

The STL2 server board includes a 10Base-T / 100Base-TX network controller that is based on the Intel® 82559 Fast Ethernet PCI Bus Controller. This device is similar in architecture to its predecessor (Intel® 82558). No external devices are required to implement an embedded network subsystem, other than TX/RX magnetics, two status Light Emitting Diodes (LEDs), and a connector. Status LEDs are not included on the external NIC connector, but there is a jumper head (6A) where status LEDs may be connected. The STL2 server board provides the ability to disable the embedded NIC in the BIOS Setup option. When disabled it is not visible to the operating system. The 82559 is a highly integrated PCI Local Area Network (LAN) controller for 10 or 100 Mbps Fast Ethernet networks. As a PCI bus master, the 82559 can burst data at up to 132 MBps. This
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high-performance bus master interface can eliminate the intermediate copy step in RX/TX frame copies, resulting in faster frame processing. The network operating system (OS) communicates with the 82559 using a memory-mapped I/O interface, PCI interrupt connected directly to the I/O Controller Hub (ICH), and two large receive and transmit FIFOs. The receive and transmit FIFOs prevent data overruns or underruns while waiting for access to the PCI bus, and also enable back-to-back frame transmission within the minimum 960ns inter-frame spacing. The figure below shows the PCI signals supported by the 82559:
AD[31::0] C/BE[3::0]_L PAR FRAME_L TRDY_L IRDY_L STOP_L DEVSEL_L IDSEL REQ_L GNT_L PCI_CLK RST_L PERR_L SERR_L PCI_INT_L

i82559 NIC

Figure 2-1. Embedded NIC PCI Signals

2.4.2.1.1

Supported Network Features

The 82559 contains an IEEE MII compliant interface to the components necessary to implement an IEEE 802.3 100Base TX network connection. The STL2 supports the following features of the 82559 controller:
· · · · · · ·

Glueless 32-bit PCI Bus Master Interface (Direct Drive of Bus), compatible with PCI Bus Specification, revis ion 2.1 / 2.2 Chained memory structure, with improved dynamic transmit chaining for enhanced performance Programmable transmit threshold for improved bus utilization Early receive interrupt for concurrent processing of receive data On-chip counters for network management Autodetect and autoswitching for 10 or 100 Mbps network speeds Support for both 10 Mbps and 100 Mbps networks, full or half duplex-capable, with backto-back transmit at 100 Mbps

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· · ·

Integrated physical interface to TX magnetics The magnetics c omponent terminates the 100Base-TX connector interface. A flash device stores the network ID. Support for Wake-on-LAN (WOL) Video Controller

2.4.2.2

The STL2 server board includes an ATI Rage IIC video controller, 4-MB video SGRAM, and support circuitry for an embedded SVGA video subsystem. The Rage IIC, 64-bit VGA Graphics Accelerator contains a SVGA video controller, clock generator, BitBLT engine, and RAMDAC. Two 512 K x 32 SGRAM chips provide 4 MB of 10ns video memory. The SVGA subsystem supports a variety of modes: up to 1280 X 1024 resolution, and up to 16.7 Million colors. It also supports analog VGA monitors, single- and multi-frequency, interlaced and non-interlaced, up to 100 Hz vertical refresh frequency. The STL2 server board provides a standard 15-pin VGA connector, and external video blanking logic for server management console redirection support. 2.4.2.2.1 Video Controller PCI Signals

The Rage IIC supports a minimal set of 32-bit PCI signals because it never acts as a PCI master. As a PCI slave, the device requires no arbitration or interrupts.
AD[31::0] C/BE[3::0]_L PAR FRAME_L TRDY_L IRDY_L STOP_L DEVSEL_L IDSEL

Rage IIC

PCI_CLK RST_L PERR_L SERR_L PCI_INT_L

Figure 2-2. Video Controller PCI Signals

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2.4.2.2.2

Video Controller PCI Commands

The Rage IIC supports the following PCI commands:
Table 2-4. Video Controller Supported PCI Commands
Rage II C Support Target Master No No No No No No No No No No No No No No No No

C/BE[3::0]_L 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate

No No Yes Yes No No Yes Yes No No Yes Yes No No No No

2.4.2.2.3

Video Modes

The Rage IIC supports all standard IBM* VGA modes. The following tables show the standard resolutions that this im plementation supports, including the number of colors and the refresh rate.
Table 2-5. Standard VGA Modes
Resolution 640x480 800x600 1024x768 1152x864 1280x1024 1600x1200 640x480 800x600 1024x768 1152x864 640x480 800x600 Refresh Rate (Hz) 200 200 150 120 100 76 200 200 150 120 200 160 Colors 256 256 256 256 256 256 65K 65K 65K 65K 16.7 M 16.7 M

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2.4.2.3

IB6566 South Bridge

The IB6566 South Bridge is a PCI device that provides multiple PCI functions in a single package: PCI-to-ISA bridge, PCI IDE interface, PCI USB controller, and power management controller. Each function within the IB6566 South Bridge has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller sharing the same PCI bus interface. On the STL2 baseboard, the primary role of the IB6566 South Bridge is to provide the gateway to all PC-compatible I/O devices and features. The STL2 server board uses the following IB6566 South Bridge features:
· · · · · · · · · ·

PCI interface IDE interface USB interface PC-compatible timer/counters and Direct Memory Access (DMA) controllers Baseboard Plug-and-Play support General purpose I/O Power management APIC and 82C59 interrupt controller Host interface for AT compatible signaling Internal only ISA bus (no ISA expansion connectors) bridge for communication with Super I/O, BIOS flash and BMC

The following sections describe each supported feature as used on the STL2 server board. 2.4.2.3.1 PCI Interface

The IB6566 South Bridge fully implements a 32-bit PCI master/slave interface, in accordance with Revision 2.2 of the PCI Local Bus Specification. On the STL2 server board, the PCI interfac e operates at 33 MHz, using the 5V-signaling environment. 2.4.2.3.2 PCI Bus Master IDE Interface

The IB6566 South Bridge acts as a PCI-based enhanced IDE 32-bit interface controller for intelligent disk drives that have disk controller electronics on-board. The server board includes a single IDE connector, featuring 40 pins (2 x 20) that support a master and a slave device. The IDE controller provides support for an internally mounted CD-ROM. The IDE controller has the following features:
· · · · · ·

Programmed Input/Output (PIO) and DMA transfer modes Mode 4 timings Transfer rates up to 33 MBps Buffering for PCI/IDE burst transfers Master/slave IDE mode Support for up to two devices

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2.4.2.3.3

USB Interface

The IB6566 South Bridge contains a USB controller and USB hub. The USB controller moves data between main memory and the two USB connectors provided. The STL2 server board provides a dual external USB connector interface. Both ports function identically and with the same bandwidth. The external connector is defined by Revision 1.0 of the USB Specification. 2.4.2.4 Compatibility Interrupt Control

The IB6566 South Bridge provides the functionality of two 82C59 Programmable Interrupt Controller (PIC ) devices, for ISA-compatible interrupt handling. 2.4.2.5 APIC

The IB6566 South Bridge integrates a 16-entry I/O APIC that is used to distribute 16 PCI interrupts. It also includes an additional 16-entry I/O APIC for distribution of legacy ISA interrupts. 2.4.2.6 Power Management

One of the embedded functions of IB6566 South Bridge is a power management controller. The STL2 server board uses this to implement ACPI-compliant power management features. STL2 supports sleep states s0, s1, s4, and s5.

2.5
2.5.1

Chipset Support Components
Legacy I/O (Super I/O) National* PC97317VUL

The National* PC97317VUL Super I/O Plug-and-Play Compatible with ACPI-Compliant Controller/Extender is used on the STL2 server board. This device provides the system with:
· · · · · · · ·

Real-time Clock (RTC) Two serial ports One parallel port Floppy disk controller (FDC) PS/2-compatible keyboard and mouse controller General purpose I/O pins Plug-and-Play functions A power management controller

The STL2 server board provides the connector interface for the floppy, dual serial ports, parallel port, PS/2 mouse and the PS/2 keyboard. Upon reset, the Super I/O (SIO) reads the values on strapping pins to determine the boot-up address configuration.

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2.5.1.1

Serial Ports

Two 9-pin connectors in D-Sub housing are provided for serial port A and serial port B. Both ports are compatible with 16550A and 16450 modes, and both are re-locatable. Each serial port can be set to one of four different COM-x ports, and each can be enabled separately. When enabled, each port can be programmed to generate edge- or level-sensitive interrupts. When disabled, serial port interrupts are available to add-in cards. 2.5.1.2 Parallel Port

The STL2 baseboard provides a 25-pin parallel port connector. The SIO provides an IEEE 1284compliant 25-pin bi-directional parallel port. BIOS programming of the SIO registers enables the parallel port and determines the port address and interrupt. When disabled, the interrupt is available to add-in cards. 2.5.1.3 Floppy Port

The FDC in the SIO is functionally compatible with floppy disk controllers CMOS 765B and 82077AA. The baseboard provides the 24-MHz clock, termination resistors, and chip selects. All other FDC functions are integrated into the SIO, including analog data separator and 16-byte FIFO. 2.5.1.4 Keyboard and Mouse Connectors

The keyboard controller is functionally compatible with the 8042A. The keyboard and mouse connectors are PS/2-compatible. 2.5.1.5 Real-time Clock

The PC97317VUL contains an MC146818-compatible real-time clock with external battery backup. The device also contains 242 bytes of general purpose battery-backed CMOS RAM. The real-time clock provides system clock and calendar information stored in non-volatile memory. 2.5.1.6 Plug-and-Play Functions / ISA Data Transfers

The PC97317VUL contains all signals for ISA compatible interrupts and DMA channels. It also provides ISA control, data, and address signals to transfer data to/from the BMC and the BIOS flash device. This ISA subsystem transfers all SIO peripheral control data to the IB6566 South Bridge as well. 2.5.1.7 Power Management Controller

The PC97317VUL component contains functionality that allows various events to allow the power-on and power-off of the system. This can be from PCI Power Management Events, the BMC , or the front panel. This circuitry is powered from stand-by voltage, which is present anytime the system is plugged into the AC outlet.

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2.5.2

BIOS Flash

The STL2 baseboard incorporates an Intel® 5V FlashFileTM 28F008SA Flash Memory component. The 28F008SA is a high-performance 8 Mbit memory that is organized as 1 MB of 8 bits each. There are 16 64-KB blocks. The 8-bit flash memory provides 1024K x 8 of BIOS and nonvolatile storage space. The flash device is directly addressed as 8-bit ISA memory. For more information, see the 5 Volt FlashFileTM Memory (28F008SA x8) Datasheet.

2.5.3

External Device Connectors

The external I/O connectors provide support for a PS/2 compatible mouse and keyboard, an SVGA monitor, two serial port connectors, a parallel port connector, a LAN port, and two USB connections.

2.6

Interrupt Routing

The STL2 server board interrupt architecture implements two I/O APICs and two PICs through the use of the integrated components in the IB6566 South Bridge component. The STL2 server board interrupt architecture allows first and second PCI interrupts to be mapped to compatible interrupt through the PCI Interrupt Address Index Register (I/O Address 0C00h) in the IB6566 South Bridge. The IB6566 South Bridge uses integrated logic to map 16 PCI interrupts to EISA/ISA. In default or Extended APIC configurations, each PCI interrupt can be independently routed to one of the 11 EISA interrupts. The interrupt mapping logic for PCI interrupts is disabled when the make bit in the corresponding I/O APIC redirection table entry is disabled (clear). This interrupt routing mechanism allows a clean transition from PIC mode to an AP IC during operating system boot.

2.6.1

Default I/O APIC

The IB6566 South Bridge integrates a 16-entry I/O APIC which is used to distribute 16 PCI interrupts.

2.6.2

Extended I/O APIC

An additional 16-entry I/O APIC is integrated in the IB6566 South Bridge to distribute EISA/ISA interrupts. This additional I/O APIC is enabled only when the IB6566 South Bridge is configured to the Extended APIC configuration.

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IRQ0/INTR IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9/SCI IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 PCIIRQ0# PCIIRQ1# PCIIRQ2# PCIIRQ3# PCIIRQ4# PCIIRQ5# PCIIRQ6# PCIIRQ7# PCIIRQ8# PCIIRQ9# PCIIRQ10# PCIIRQ11# PCIIRQ12# PCIIRQ13# PCIIRQ14# PCIIRQ15#

PIC IB6566 South Bridge

PCI Interrupt Router
IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15

Figure 2-3. STL2 Baseboard Interrupt Routing Diagram (PIC mode)

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Timer Keyboard Cascade Serial Port2/ISA Serial Port1/ISA ISA Floppy/ISA Parallel/ISA RTC SCI/ISA ISA ISA Mouse/ISA Coprocessor Err P_IDE/ISA Not Used SCSI PORT A SCSI PORT B LAN VGA Slot02 INTA Slot03 INTA Slot04 INTA Slot05 INTA Slot06 INTA Slot01 INTA SLOT B C D 02 03 04 05 06 01

IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 PIRQ0(16) PIRQ1(17) PIRQ2(18) PIRQ3(19) PIRQ4(20) PIRQ5(21) PIRQ6(22) PIRQ7(23) PIRQ8(24) PIRQ9(25) PIRQ10(26) PIRQ11(27) PIRQ12(28) PIRQ13(29) PIRQ14(30) PIRQ15(31)

Figure 2-4. STL2 Baseboard Interrupt Routing Diagram (Symmetric mode)

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2.6.3

PCI Ids

The STL2 server board PCI IDs are defined as follows:
Table 2-6. STL2 PCI IDs
Device NB6635 North Bridge 3.0LE ATI* Rage IIC Intel 82559 Adaptec* AIC-7899 Slot 1 (32 bit) Slot 2 (32 bit) Slot 2 (32 bit) Slot 2 (32 bit) IB6566 South Bridge Slot 2 (32 bit) Slot 2 (32 bit) Bus Number [23:16] 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Device Number [15:11] 00000b 00010b 00011b 00100b 00110b 00111b 01000b 01001b 01111b 01010b 01011b Slot ID Signal P32_AD18 P32_AD 19 P32_AD20 P32_AD22 P32_AD23 P32_AD24 P32_AD25 P32_AD31 P32_AD26 P32_AD27

Note: Do not change the BUSNUM register (Offset 44h) in the NB6635 North Bridge 3.0 LE from the default value.

2.6.4

Relationship between PCI IRQ and PCI Device

The relationship between PCI IRQ and PCI devices are defined as follows on the STL2 server board:
Table 2-7. STL2 Relationship between PCI IRQ and PCI Device
PCI IRQ PCI IRQ 0 PCI IRQ 1 PCI IRQ 2 PCI IRQ 3 PCI IRQ 4 PCI IRQ 5 PCI IRQ 6 PCI IRQ 7 PCI IRQ 8 PCI IRQ 9 PCI IRQ 10 PCI IRQ 11 PCI IRQ 12 PCI Device Adaptec AIC-7899 SCSI Channel A Adaptec AIC-7899 SCSI Channel B Intel 82559 ATI Rage IIC PCI Slot 2 (INTA) PCI Slot 3 (INTA) Not Used PCI Slot 4 (INTA) PCI Slot 5 (INTA) PCI Slot 6 (INTA) PCI Slot 1 (INTA) PCI Slot 1 (INTB), PCI Slot 2 (INTB), PCI Slot 3 (INTC), PCI Slot 4 (INTB), PCI Slot 5 (INTC), PCI Slot 6 (INTD) PCI Slot 1 (INTC), PCI Slot 2 (INTC), PCI Slot 3 (INTD), PCI Slot 4 (INTC), PCI Slot 5 (INTD), PCI Slot 6 (INTB)

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PCI IRQ 13

PCI Slot 1 (INTD), PCI Slot 2 (INTD), PCI Slot 3 (INTB), PCI Slot 4 (INTC), PCI Slot 5 (INTD), PCI Slot 6 (INTB)

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Server Management

3.

Server Management

This section describes the features of the server management subsystem for the STL2 server board. The server management subsystem consists of the BIOS, hardware, and firmware features built into the server board. These features provide hardware monitoring, c ontrol, and logging to improve the reliability, availability, and serviceability of the server system. The server management subsystem conforms to the IPMI (Intelligent Platform Management Interface) v1.0 specification. IPMI defines a standardized, abstrac ted, message-based interface between system management software and the platform management hardware. The following comprise the major elements of the server management architecture for the STL2 server board.
· · · ·

Baseboard Management Controller (BMC ) Sensors Sensor Data Record (SDR) Repository and System Event Log (SEL) Field Replaceable Unit (FRU) Information

3.1

Baseboard Management Controller

The STL2 server management functionality is concentrated in the BMC . The BMC is comprised of a Dallas* Semiconductor DS80CH11 (or equivalent) microcontroller and associated circuitry located on the STL2 server board. The BMC and associated circuits are powered from a 5-V DC standby voltage, which remains active when system power is switched off, but the AC power source is still on and connected. A major function of the BMC is to autonomously monitor system management events and log the occurrence in the nonvolatile System Event Log (SEL). The events being monitored include over/under temperature and over/under voltage conditions, fan failure, or chassis intrusion. To enable accurate monitoring, the BMC maintains the nonvolatile Sensor Data Record (SDR) from which sensor information can be retrieved. The BMC provides an ISA host interface to SDR sensor information, so that software running on the server can poll and retrieve the server's current status. The BMC also provides the interface to the monitored information and SEL that System Management Software, such as Intel® Server Control, uses to poll and retrieve the platform status. The BMC performs the following functions:
· · · · · · · ·

Monitors server boad temperature and voltage Monitors processor presence and controls Fault Resilient Boot (FRB) Detects and indicates baseboard fan failure Manages the SEL interface Manages the SDR Repository interface Monitors the SDR/SEL timestamp clock Monitors the s ystem management watchdog timer Monitors the periodic SMI timer
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· · ·

Monitors the event receiver Controls secure mode, inlucluding video blanding, diskett write-protect monitoring, and fornt panel lock/unlock initiation Controls Wake-on-Lan via Magic Packet* support

3.2

Hardware Sensors

The following table lists the hardware sensors present on the STL2 server board.
Table 3-1. STL2 Hardware Sensors
Sensor Number 01h 02h 03h 20h 21h 22h 23h 24h 25h 29h 2Ah 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 40h 41h 42h 60h 61h 70h 71h 72h 7Fh 90h Power Distribution Board Power Distribution Board Supply 1 Power Distribution Board Supply 2 Power Redundancy Lost Chassis Intrusion ID Processor Voltage (Discrete) Fan Voltage Sensor Type Temperature Monitoring Device ADM1024 Temperature Processor 1 internal Processor 2 internal 3.3 V 5V 12 V 3.3 V Standby Processor 1 Processor 2 1.5 V 2.5 V SCSI-A 2.85 V SCSI-B 2.85 V SCSI-A Vref1 SCSI-A Vref2 SCSI-A Vref3 SCSI-B Vref1 SCSI-B Vref2 SCSI-B Vref3 Performance Lags Baseboard Fan 1 Baseboard Fan 2 Baseboard Fan 3 Processor 1 State Processor 2 State Soft Power Control Failure (bit 5) Interlock Power Power supply Failure detected (bit 1) Power supply Failure detected (bit 1) Redundancy Lost (bit 1) Redundancy Regained (bit 0) Drive Bay Intrusion (bit 1) LAN Leash Lost (bit 4)

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Sensor Number 91h 92h 93h 94h 95h 96h 97h

Sensor Type

Monitoring Device LAN Leash Lost (bit 4)

Security Violation Memory Error POST Memory Resize BIOS POST (Error) Code Log Disable System Event Critical Interrupt

Secure Mode Violation Attempt (bit 0) ECC multiple bit error (bit 1) ECC single bit error (bit 0)

Log Area Reset / Cleared (bit 2) ECC single bit Error Disable (bit 0) Original Equipment Manufacturer (OEM) System Event (Hard Reset) (bit 1) System PCI SERR (bit 5) PCI PERR (bit 4) Front Panel NMI (Dump SW) (bit 0) Reset Button (bit 2) Sleep Button (bit 1) Power Button (bit 0) User requested Preboot Execution Environment (PXE) boot (bit 3) Initiated by power up (bit 0) PXE Server not found (bit 2) No bootable media (bit 0)

98h

Button

99h 9Ah

No Processor or Termination Board Boot Init

9Bh 9Ch 9Dh 9Fh

Boot Error OS Boot OS Stop ACPI State

Sleeping in S1 state (bit 8) G3/Mechanical Off (bit 7) S5 / G2 Soft Off (bit 5) S4 (bit 4) BMC Watchdog Timer (WDT) Timeout Processor Area Intrusion (bit 4) Drive Bay Intrusion (bit 1) SMI Stall State

A0h C0h C1h F3h

BMC Watchdog Chassis Intrusion ID (Disable) Chassis Intrusion ID Server Management Interrupt (SMI) State

The following table provides a list of System Event Log (SEL) events supported by the STL2 server board.
Table 3-2. STL2 Supported System Event Log (SEL) events
Sensor Type Reserved Temperature Sensor Type Code 00h 01h Sensor -Specific Event Offset ­ ­ Reserved Temperature An error occurred at thermal sensors Remarks

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Sensor Type Voltage

Sensor Type Code 02h

Sensor -Specific Event Offset ­ 01h Voltage Performance Lags

Remarks An error occurred at voltage sensors In the single-end event mode, even if SCSI is available for a different mode event. An error occurred at fan sensors. Front cover has been opened or closed Side (Chassis) cover has been opened or closed.

Fan Physical Security

04h 05h

­ 01h 03h 04h

Fan Drive Bay Intrusion Processor area intrusion LAN Connection Lost

(System has LAN cable been unplugged has been from LAN) plugged in or unplugged. Platform 06h Security Violation Attempt 00h Secured Mode Violation Attempt Pre-boot Password Violation (network boot Password) IERR Thermal Trip FRB1/BIST Failure FRB3/Processor Startup/Initialization failure (Processor didn't start) Processor disabled Correctable ECC Uncorrectable ECC POST Memory Resize POST Error 00h 01h 02h 03h System Event 12h 00h 01h Correctable Memory Error Logging Disabled Power/sleep switch has been activated while in Secure Mode Bad Password at PXE Boot Processor IERR has occurred Processor Thermal Trip has occurred BIST Error has occurred FRB3 Timeout has been detected A processor has been disabled ECC 1-bit error occurred ECC 2-bit error occurred Displays the total amount of memory after memory failure POST Error occurred Displays ECC single bit error monitoring disabled

03h Processor 07h 00h 01h 02h 04h

08h Memory POST Memory Resize POST Error Event Logging Disabled 0Ch 0Eh 0Fh 10h 00h 01h

Event `Type' Logging Disabled Monitoring of a certain event type has been disabled Log Area Reset/Cleared All Event Logging Disabled System Reconfigured Displays the SEL area cleared. Monitor for the entire BMC has been disabled. Setup change has occurred

OEM System Boot Event (Hard Cold reset has been issued Reset)

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Sensor Type

Sensor Type Code

Sensor -Specific Event Offset 00h 02h 04h 05h Front Panel Non-Maskable Interrupt (NMI) Dump Switch I/O channel check NMI PCI SERR PCI PERR Power Button Sleep Button Reset Button Processor / Terminator Missing 03h 04h User requested PXE boot Automatic boot to diagnostic No bootable media PXE Server not found C: boot completed PXE boot completed

Remarks Dump switch has been activated ISA I/O Check has occurred. PCI SERR occurred PCI PERR occurred Power switch has been activated Sleep switch has been activated Reset switch has been activated Processor / Terminator is not mounted correctly PXE (Network) Booted When the maintenance Utility Booted Boot Media does not exist. PXE Server is not fo und ESM Pro installed OS has been booted PXE boot for the express server is finished (not supported) Maintenance Utility has been booted (not supported) The server has been booted (not supported) OS stalled during startup OS stalled during startup DC is ON S1 Sleep State

Critical Interrupt 13h

Button

14h

00h 01h 02h

Module / Board System Boot Initiated

15h 1Dh

Boot Error

1Eh

00h 02h 00h 02h

03h 04h OS Critical Stop 20h 00h 01h System ACPI Power State 22h 00h 01h

Diagnostic boot com pleted CD-ROM boot completed Stop during OS load / Initialization Run-ti me Stop S0 / G0 Working S1 "sleeping with system hardware and processor context Maintained" S4 "non-volatile sleep / suspend -to disk" S5 / G2 "soft-off" G3 / Mechanical Off Sleeping (cannot differentiate between S1-S3) Hard Reset Power Down

04h 05h 07h 08h

S4 Sleep State DC is OFF AC is OFF SUSC# OS has been asserted without the instruction to sleep POST/Boot monitor timed out OS WDT shut down after the monitor timeout

Watchdog 2

23h

01h 02h

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Sensor Type

Sensor Type Code F3h F5h

Sensor -Specific Event Offset 08h Timer Interrupt SMI Timeout 00h Communication Error

Remarks OS WDT monitor timed out SMI# has been asserted for more than ten seconds Communication is unavailable even though the BMC is in communication status SMBus Device does not answer. SMBus Timeout error

SMI Timeout Emergency Management Port (EMP) Sensor Failure

F6h

00h 01h 02h

I2C Bus Device Address Not Acknowledged I2C Bus Timeout

I2C Bus Device Error Detected Other access errors

OEM Reserved

F7h - FFh

3.3

ACPI
Configuration and Power Interface (ACPI)-aware operating s ystem can place the state where the hard drives spin down, the sytem fans stop, and all processing is state the power supply is still on and the processors still dissipate some power, power supply fan and processor fans are still running.

The Advance system into a halted. In this such that the

Note: ACPI requires an operating system that supports this feature. The ACPI sleep states discussed below are defined as:
· · ·

·

s0: Normal running state s1: Processor sleep state. No content is lost in this state and the processor caches maintain coherency. s4: Hibernate or Save to Disk. The memory and machine state are saved to disk. Pressing the power button or another wakeup event restores the system state from the disk and resumes normal operation. This assumes that no hardware changes were made to the system while it was off. s5: Soft off. Only the RTC section of the chip set and the BMC are running in this state.

The STL2 server board supports sleep states s0, s1, s4, and s5. When the server board is operating in ACPI mode, the OS retains control of the system and the OS policy determines the entry methods and wake up sources for each sleep state ­ s leep entry and wake up event capabilites are provided by the hardware but are enabled by the OS. With future versions of Microsoft* Windows* 9X that support ACPI, the system BIOS supports only sleep states s0, s1, and s5. With future versions of Microsoft Windows NT * that support ACPI, the system BIOS will support sleep states s0, s1, s4, and s5.

3.4

AC Link Mode

The AC link mode allows the system to monitor its AC input power so that if AC input power is lost and then restored, the system returns to one of the following preselected settings:
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· ·

Last State (Factory Default Setting) Stay Off

The AC link mode settings can be changed by running the BIOS Setup Utility.

3.5

Wake On LAN Function

The remote power-on function turns on the system power by way of a network or modem. If the system power is set to Off, it can be turned on remotely by sending a specific packet from the main computer to the remote system. Note: The standard default value of the remote power-on function is "Disabled". The Wake-onLAN / Ring function can changed by setting the option to "Enabled" in the BIOS Setup Utility.

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4.

Basic Input Output System (BIOS )

This section describes BIOS embedded software for the STL2 board set. The BIOS contains standard PC-compatible basic input/output (I/O) services, standard Intel® server features, plus the STL2 system -specific hardware configuration routines and register default settings, embedded in Flash read-only memory (ROM). This section also describes BIOS support utilities (not ROM-resident) that are required for system configuration and flash ROM update. The BIOS is implemented as firmware that resides in the flash ROM. Support for applicable baseboard peripheral devices (SCSI, NIC, and video adapters), which is also loaded into the baseboard flash ROM, is not specified in this document. Hooks are provided to support adding BIOS code for these adapters; the binaries must be obtained from the peripheral device manufacturers and loaded into the appropriate locations.

4.1

BIOS Overview

The term BIOS, as used in the context of this section, refers to the system BIOS, the BIOS Setup and option ROMs for on-board peripheral devices that are contained in the system flash. System BIOS controls basic system functionality using stored configuration values. The terms flash ROM, system flash, and BIOS flash may be used interchangeably in this section. The term BIOS Setup refers to the flash ROM-resident setup utility that provides the user with control of configuration values stored in battery-backed CMOS configuration RAM. The System Setup Utility (SSU), which also provides this functionality, is discussed in a separate document. BIOS Setup is closely tied with the system BIOS and is considered a part of BIOS. Phoenix Phlash* (PHLASH.EXE ) is used to load predefined areas of flash ROM with Setup, BIOS, and other code/data. The following is the break-down of the STL2 product ID string:
· · · · · · ·

4-byte board ID, `STL2' 1-byte board revision, starting from `0' 3-byte OEM ID, `86B' for standard BIOS 4-byte build number 1-3 byte describing build type (D for development, A for Alpha, B for Beta, Pxx for production version xx) 6-byte build date in yymmdd format 4-bytes time in hhmm format

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4.1.1

System BIOS

The system BIOS is the core of the flash ROM-resident portion of the BIOS. The system BIOS provides standard PC-BIOS services and support for some new industry standards, such as the Advanced Configuration and Power Interface Specification, Revision 1.0 and Wired For Management Baseline Specification, Revision 2.0. In addition, the system BIOS supports certain features that are common across all the Intel servers. These include:
· · · · · · · ·

Security Intel Multi-Processor Specification (MPS) support Server management and error handling CMOS configuration RAM management OEM customization PCI and Plug and Play (PnP) BIOS interface Console redirection Resource allocation support

BIOS setup is embedded in flash ROM and provides the means to configure on-board hardware devices and add-in cards. For more information, refer to Section 4.2, Setup Utility.

4.1.2

Flash Update Utility

The system BIOS and the setup utility are resident in partitioned flash ROM. The device is incircuit reprogrammable. On the STL2 platform, 1 MB of flash ROM is provided. The STL2 BIOS does not support a SecureBIOS feature like some server products from Intel. This is because the addition of SecureBIOS increases boot time, and complexities, and does not provide compelling benefits for the STL2 platform. The Phoenix Phlash Utility may be used to reprogram the BIOS operational code located in the flash ROM. A BIOS image is provided on a diskette in the form of a binary file that is read by the Phoenix Phlash Utility. Baseboard revisions may create hardware incompatibilities and may require different BIOS code. 4.1.2.1 System Flash ROM Layout

The flash ROM contains system initialization routines, BIOS strings, BIOS Setup, and run-time support routines. The exact layout is subject to change, as determined by Intel. A 16-KB user block is available for user ROM code and another 128-KB block is available for custom logos. The flash ROM also contains compressed initialization code for on-board peripherals such as SCSI, NIC, and video controllers. The BIOS image contains all the BIOS components at appropriate locations. The Phoenix Phlash Utility can be used to reprogram the BIOS operational code areas. At run time, none of the flash blocks is visible at the aliased addresses below 1 MB due to shadowing. Intel reserves the right to change the flash map without notice. A 64-KB parameter block in the flash ROM is dedicated to storing configuration data that controls extended system configuration data (ESCD), on-board SCSI configuration, OEM configuration areas, etc. The block is partitioned into separate areas for logically different data. Application
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software must use standard advanced programmable interrupts (APIs) to access these areas and may not access the data directly.

4.2

Setup Utility

This section describes the ROM resident setup utility that provides the means to configure the platform. The setup utility is part of the system BIOS and allows limited control over on-board resources such as the parallel port and mouse. The following topics are covered below:
· · ·

Setup utility operation Configuration CMOS RAM definition Function of the CMOS clear jumper

4.2.1

Configuration Utilities Overview

Configuration of on-board devices is done using the setup utility that is embedded in flash ROM. Setup provides sufficient configuration functionality to boot a system diskette or CD-ROM. The System Setup Utility (SSU) , which is discussed in a separate document, is released on diskette or CD-ROM. Setup is always provided in flash for basic system configuration. The configuration utilities modify CMOS RAM and Non-Volatile Random Access Memory (NVRAM) under direction of the user. The BIOS POST routines and the BIOS Plug-N-Play Autoconfiguration Manager accomplish the actual hardware configuration. The configuration utilities always update a checksum for both areas, so that any potential data corruption is detectable by the BIOS before the hardware configuration takes place. If data is corrupted, the BIOS requests that the user reconfigure the system and reboot.

4.2.2

Setup Utility Operation

The ROM-resident setup utility configures only on-board devices. The setup utility screen is divided into four functional areas. Table 4-1 describes each area:
Table 4-1. Setup Utility Screen
Functional Area Keyboard Command Bar Menu Selection Bar Description Located at the bottom of the screen. This bar displays the keyboard commands supp orted by the setup utility. Located at the top of the screen. Displays the various major menu selections available to the user. The server setup utility major menus are: Main Menu, Advanced Menu, Security Menu, System Menu, Boot Menu, and the Exit Menu. Each Option Menu occupies the left and center sections of the screen. Each menu contains a set of features. Selecting certain features within a major Option Menu drops you into submenus. Located at the right side of the screen is an item -specific Help screen.

Options Menu

Item Specific Help Screen

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4.2.2.1

Entering Setup Utility

During POST operation, the user is prompted to enter Setup using the F2 function key as follows: Press to enter Setup After the F2 key is pressed, a few seconds might pass before Setup is entered while POST finishes test and initialization functions that must be completed before Setup can be entered. When Setup is entered, the Main Menu options page is displayed. 4.2.2.2 Keyboard Command Bar

The bottom portion of the screen provides a list of commands that are used for navigating the Setup utility. These commands are displayed at all times, for every menu and submenu. Each Setup menu page contains a number of features. Except those used for informative purposes, each feature is associated with a value field. This field contains user-selectable parameters. Depending on the security option chosen and in effect via password, a menu feature's value can be changeable or not. If a value is cannot be changed due to insufficient security privileges or other reasons, the feature's value field is inaccessible. The Keyboard Command Bar supports the following: F1 Help Pressing F1 on any menu invokes the general Help window. This window describes the Setup key legend. The up arrow, down arrow, Page Up, Page Down, Home, and End keys scroll the text in this window. Enter Execute Command The Enter key is used to activate submenus when the selected feature is a submenu, or to display a pick list if a selected feature has a value field, or to select a subfield for multi-valued features like time and date. If a pick list is displayed, the Enter key will undo the pick list, and allow another selection in the parent menu. ESC Exit The ESC key provides a mechanism for backing out of any field. This key will undo the pressing of the Enter key. When the ESC key is pressed while editing any field or selecting features of a menu, the parent menu is re-entered. When the ESC key is pressed in any submenu, the parent menu is re-entered. When the ESC key is pressed in any major menu, the exit confirmation window is displayed and the user is asked whether changes can be discarded. Select Item The up arrow is used to select the previous value in a pick list, or the previous feature in a menu item's option list. The selected item must then be activated by pressing the Enter key. Select Item The down arrow is used to select the next value in a menu item's option list, or a value field's pick list. The selected item must then be activated by pressing the Enter key.

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Select Menu The left and right arrow keys are used to move between the major menu pages. The keys have no affect if a submenu or pick list is displayed. F5/­ Change Value The minus key and the F5 function key are used to change the value of the current item to the previous value. These keys scroll through the values in the associated pick list without displaying the full list. F6/+ Change Value The plus key and the F6 function key are used to change the value of the current menu item to the next value. These keys scrolls through the values in the associated pick list without displaying the full list. On 106-key Japanese keyboards, the plus key has a different scan code than the plus key on the other keyboard, but it still has the same effect. F9 Setup Defaults Pressing the F9 key causes the following to appear: Setup Confirmation Load default configuration now? [Yes] [No] If "Yes" is selected and the Enter key is pressed, all Setup fields are set to their default values. If "No" is selected and the Enter key is pressed, or if the ESC key is pressed, the user is returned to where s/he was before the F9 key was pressed, without affecting any existing values. F10 Save and Exit Pressing F10 causes the following message to appear: Setup Confirmation Save Configuration changes and exit now? [Yes] [NO] If "Yes" is selected and the Enter key is pressed, all changes are saved and Setup is exited. If "No" is selected and the Enter key is pressed, or the ESC key is pressed, the user is returned to where s/he was before the F10 key was pressed, without affecting any existing values. 4.2.2.3 Menu Selection Bar

The Menu Selection Bar is located at the top of the screen. It displays the various major menu selections available to the user:
· · ·

Main Menu Advanced Menu Security Menu
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· · ·

System Menu Boot Menu Exit Menu

These and associated submenus are described below. 4.2.2.4 Main Menu Selections

The following tables describe the available functions on the Main Menu, and associated submenus . Default values are highlighted.
Table 4-2. Main Menu Selections
Feature System Time System Date Diskette A Choices or Display Only HH:MM:SS MM/DD/YYYY 1.44 / 1.25 MB 3.5" / Disabled Description Sets the system time (hour, minutes, seconds, on 24 hour clock). Sets the system date (month, day, year). Selects the diskette type. Note: 1.25-MB, 3.5 -inch references a 1024-byte/sector Japanese media format. To support this type of media format requires a 3.5 -inch, 3 -mode diskette drive. Selects the diskette type. Note: 1.25-MB, 3.5 -inch references a 1024-byte/sector Japanese media format. To support this type of media format requires a 3.5-inch, 3 -mode diskette drive. Delays first access to disk to ensure the disk is initialized by the BIOS before any accesses. User Setting

Diskette B

1.44 / 1.25 MB 3.5" / Disabled

Hard Disk Pre-Delay

Disabled 3 Seconds 6 Seconds 9 Seconds 12 Seconds 15 Seconds 21 Seconds 30 Seconds

Primary Ma ster Primary Slave Processor Language English (US) French German Spanish Italian

Displays IDE device selection. Enters submenu if selected. Displays IDE device selection. Enters submenu if selected. Enters Processor Settings submenu if selected. Selects which language BIOS displays. Note: This feature immediately changes to the language BIOS selected.

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Table 4-3. Primary Master and Slave Adapters Submenu Selections
Choices or Display Only Feature Type Auto None CD-ROM ATAPI Removable IDE Removable Other ATAPI User Disable 2 Sectors 4 Sectors 8 Sectors 16 Secto rs Disabled Enabled Disabled Enabled Standard Fast PIO 1 Fast PIO 2 Fast PIO 3 Fast PIO 4 FPIO 3/ DMA 1 FPIO 4 / DMA 2 Disabled Enabled Description Select the type of device that is attached to the IDE channel If User is selected, the user will need to enter the parameters of the IDE device (cylinders, heads and sectors). User Setting

Mult-Sector Transfers

Specifies the number of sectors that are transferred per block during multiple sector transfers.

LBA Mode Control

Enable/Disable Logical Block Addressing instead of cylinder, head, sector addressing. Enable/Disable 32-Bit IDE data transfers Select the method of moving data to and from the hard drive. (If Type: Auto is select, optimum transfer mode will be selected)

32 Bit I/O Transfer Mode

Ultra DMA Mode

Enable/Disable Ultra DMA mode (If Type: Auto is select, optimum transfer mode will be selected)

Table 4-4. Processor Settings Submenu Selections
Choices or Display Only Feature Processor Speed Processor 1 Type Cache Ram Processor 2 Type Cache Ram Processor #1 Status Processor #2 Status Clear Processor Errors Processor Error Pause XXX XXX XXXKB XXX XXXKB Normal 1 Normal 1 Press Enter Enabled Disabled Description (Display Only). Indicates the processor speed. (Display Only). Indicates the CPUID of the installed processor. (Display Only). Indicates the cache RAM size. (Display Only). Indicates the CPUID of the installed processor. (Display Only). Indicates the cache RAM size. (Display Only) (Display Only) Clears the processor error information. If enabled, the POST operation pauses if a processor error occurs. User Setting

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Processor Serial Number Note: 1.

Disabled Enabled

Disables/Enables Processor Serial Number.

Possible Values: Normal, None, or Error.

4.2.2.5

Advanced Menu Selections

The following tables describe the menu options and associated submenus available on the Advanced Menu. Please note that MPS 1.4 / 1.1 selection is no longer configurable. The BIOS will always build MPS 1.4 tables.
Table 4-5. Advanced M enu Selections
Choices or Display Only Feature Memory Reconfiguration Peripheral Configuration PCI Device Option ROM Description Refer to Memory Reconfiguration Submenu. Refer to Peripheral Reconfiguration Submenu. Refer to PCI Device Submenu. Refer to Option ROM Submenu. It Disables/Enables the Option ROM BIOS on the PCI Bus. Refer to Numlock Submenu. No Yes Other PnP OS Clears the Extended System Configuration Data if selected. Selects the type of operating system that will be used most. User Setting

Numlock Reset Configuration Data Installed OS

Table 4-6. Memory Reconfiruation Submenu Selections
Choices or Display Only Feature System Memory Extended Memory DIMM #1 Status DIMM #2 Status DIMM #3 Status DIMM #4 Status Clear DIMM Errors DIMM Error Pause XXX KB XXXXXX KB Normal Normal Normal Normal
1 1 1 1

Description (Display Only). Indicates the total capacity of the basic memory. (Display Only). Indicates the total capacity of the extended memory. (Display Only) (Display Only) (Display Only) (Display Only) Clears the DIMM group error status information. If enabled, the POST operation pauses if a DIMM error occurs.

User Setting

Press Enter Enabled Disabled

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Note: 1. Possible Values: Normal, None, or Error (DIMM Row Error).

Table 4-7. Peripheral Configuration Submenu Selections
Feature Serial Port 1: (COM 1) Choices or Display Only Disabled 3F8, IRQ3 3F8, IRQ4 2F8, IRQ3 2F8, IRQ4 3E8, IRQ3 3E8, IRQ4 2E8, IRQ3 2E8, IRQ4 Auto Disabled 3F8, IRQ3 3F8, IRQ4 2F8, IRQ3 2F8, IRQ4 3E8, IRQ3 3E8, IRQ4 2E8, IRQ3 2E8, IRQ4 Auto Disabled 378, IRQ5 378, IRQ7 278, IRQ5 278, IRQ7 3BC, IRQ5 3BC, IRQ7 Auto Output only Bi-directional EPP ECP, DMA1 ECP, DMA3 Disabled Enabled Disabled Enabled Auto Detect Description Disables serial port 1 or s elects the base address and interrupt (IRQ) for serial port 1. User Setting

Serial Port 2: (COM 2)

Disables serial port 2 or selects the base address and inte rrupt (IRQ) for serial port 2.

Parallel Port

Disables the parallel port or selects the base address and interrupt (IRQ) for the Parallel port.

Parallel Mode

Selects the parallel port operation mode.

Diskette Controller Mouse

Disables/Enables the floppy disk controller. Disabled prevents any installed PS/2 mouse from functioning, but frees up IRQ12. Enabled forces the PS/2 mouse port to be enabled regardless if a mouse is present. Auto Detect enables the PS/2 mouse only if present. OS Controlled is displayed if the OS controls the mouse.

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Feature SCSI Controller LAN Controller VGA Controller USB Controller

Choices or Display Only Disabled Enabled Disabled Enabled Enabled Disabled Disabled Enabled

Description Disables/Enables on -board SCSI controller. Frees resources. Disables/Enables on -board LAN controller. Frees resources. Disables/Enables on -board Video controller. Frees resources. Enables/Disables on -board USB controller. Frees resources.

User Setting

Table 4-8. PCI Device Submenu Selections
Feature PCI IRQ1 through PCI IRQ14 Choices or Display Only Disabled Auto Select IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 Description Specify which PIC IRQ a certain PCI IRQ maps to. User Setting

Table 4-9. Option ROM Submenu Selections
Feature Onboard SCSI Choices or Display Only Enabled Disabled Description Disables/Enables option ROM expansion for the on-board SCSI option ROM. This must be enable if a boot device is connected to the on-board device. Disables/Enables option ROM expansion for the on-board LAN option ROM. Disables/Enables the expansion of the option ROM for devices in PCI slot 1 Disables/Enables the expansion of the option ROM for devices in PCI slot 2 Disables/Enables the expansion of the option ROM for devices in PCI slot 3 Disables/Enables the expansion of the option ROM for devices in PCI slot 4 Disables/Enables the expansion of the option ROM for devices in PCI slot 5 Disables/Enables the expansion of the option ROM for devices in PCI slot 6 Disables/Enables the expansion of the option ROM for devices in PCI slot 7 User Setting

Onboard LAN

Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled

PCI Slot 1 PCI Slot 2 PCI Slot 3 PCI Slot 4 PCI Slot 5 PCI Slot 6 PCI Slot 7

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Table 4-10. Numlock Submenu Selections
Feature Numlock Choices or Display Only Auto On Off Disabled Enabled 2/sec 6/sec 10/sec 13.3/sec 18.5/sec 21.8/sec 26.7/sec 30/sec 0.25 sec 0.5 sec 0.75 sec 1 sec Description Selects the power-on state for Numlock. User Setting

Key Click Keyboard Auto -repeat Rate

Disables or enables keyclick. Selects key repeat rate.

Keyboard Auto -repeat Delay

Selects delay before key repeat.

4.2.2.6

Security Menu Selections
Table 4-11. Security Menu Selections

Feature Supervisor Password is

Choices or Display Only Clear

User Password is

Clear

Set Supervisor Password

Press Enter

Set User Password

Press Enter

Password on Boot Fixed Disk Boot Sector

Disabled Enabled Normal Write Protect

Description (Display only). Once set, this can be disabled by setting it to a null string, or by clearing password jumper on system board. (Display only). Once set, this can be disabled by setting it to a null string, or by clearing password jumper on system board Supervisor password controls access to the setup utility. When the key is pressed, the user is prompted for a password; press ESC key to abort. Once set, this can be disabled by setting it to a null string, or by clearing password jumper on system board. When the key is pressed, the user is prompted for a password; press ESC key to abort. Once set, this can be disabled by setting it to a null string, or by clearing password jumper on system board. Disables or enables password entry on boot. Write protects boot sector on hard disk.

User Setting

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Feature Diskette Access Secure Mode

Choices or Display Only User Supervisor

Description Controls access to diskette drives. See Secure Mode Submenu. Submenu can only be entered if supervisor and user password is set. Determines wheth er power switch will function from front panel Determines whether on-board SCSI Option ROM will allow the user to enter adapter configuration with -A

User Setting

Power Switch Mask Option ROM Menu Mask

Masked Unmasked Unmasked Masked

Table 4-12. Secure Mode Submenu Selections
Feature Secure Mode Timer Choices or Display Only Disabled 1 Min 2 Min 5 Min 10 min 30 min 1 hr 2 hr Disabled Enabled Description Period of keyboard and mouse inactivity before secure mode is activated and a password is required gain access. User Setting

Secure Mode HotKey

Enables/Disables the ability to lock the system with a + + combination. The key can be selected and submenu appe ars when enabled. A password is required to gain access. Enables/Disables secure boot. The system will boot as normal, but a password is required to access the system using any PS/2 device Enables/Disables floppy drive write protection. If enabled, a password is required to write to a floppy.

Secure Mode Boot

Disabled Enabled

Floppy Write Protect

Disabled Enable

4.2.2.7

System Hardware Menu Selections
Table 4-13. Server Menu Selections
Feature Choices or Display Only Power On Last State Stay Off Press Enter Description See Wake On Events submenu. Selects power retention mode if AC power is lost a regained. Select to clear the system Error Log. If Clear OK, then display "System Event User Setting

Wake On Events AC Link

Error Log Initialization

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Log Cleared!" If Clear failed, then display "System Event Log Not Cleared!" Console Redirecti on Assert NMI on PERR Disabled Enabled See Console Redirecti on Submenu. Enables PCI PERR support.

Table 4-14. Wake On Events Submenu Selections
Feature Wake On LAN Wake On Ring Choices or Display Only Enabled Disabled Enabled Disabled Description Enables/Disables Wake-on-LAN support. Enables/Disables Wake-on-Ring support. User Setting

Table 4-15. Console Redirection Submenu Selections
Feature Serial Port Address Choices or Display Only Disabled Serial Port 2 (3F8h/IRQ4) Serial Port 2 (2F8h/IRQ3) Description If enabled, the console will be redirected to this port. If console redirection is enabled, this address must match the settings of serial port 2. Enables the specified baud rate. Selects flow control. Indicate whether the console is connected directly to the system or if a modem is used to connect. User Setting

Baud Rate Flow Control Console Connection

57.6 K 19.2 K No Flow Control XON/OFF Direct Via Modem

4.2.2.8

Boot Menu Selections

Boot Menu options allow the user to select the boot device. The following table is an example of a list of devices ordered in priority of the boot invocation. Items can be re-prioritized by using the up and down arrow keys to select the device. Once the device is selected, use the plus (+) key to move the device higher in the boot priority list. Use the minus (-) key to move the device lower in the boot priority list.
Table 4-16. Boot Menu Selections
Feature Boot-Time Diagnostic Screen Enabled Choices or Display Only Disabled Enable/Disable boot-time diagnostic screen. Splash screen is displayed over the diagnostic screen when is Description User Setting

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option is Disabled. Boot Device Priority Hard Drive Removable Devices See Boot Device Priority Submenu See Hard Drive Submenu See Removable Devices Submenu

Table 4-17. Boot Device Priority Selections
Boot Priority 1 2 3 4 Device ATAPI CD-ROM Drive Removable Devices Hard Drive Intel UNDI, PXE -2.0 Description Attempts to boot from an ATAPI CD-ROM drive. Attempts to boot from a removable device. Attempts to boot from a hard drive device. Attempts to boot from a PXE server. User Setting

Table 4-18. Hard Drive Selections
Boot Priority 1 Device AIC-7899,CH B ID 1
1

Description Select the order in which each drive is attempted to be used as the boot device.
1 1

User Setting

2 3 4 Note: 1.

AIC-7899, CH A, ID 9

AIC-7899, CH B, ID 4

Bootable Add-in Cards These selections will change depending on the system configuration

Table 4-19. Removable Devices Selections
Boot Priority 1 Device Legacy Floppy Drives Description Select the order in which each removable device is attempted to be used as the boot device.1 User Setting

Note: 1. These selections will change depending on the system configuration

4.2.2.9

Exit Menu Selections

The following menu options are available on the Exit menu. Use the up and down arrow keys to select an option, then press the Enter key to execute the option.

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Table 4-20. Exit Menu Selections
Option Exit Savi ng Changes Exit Discarding Changes Load Setup Defaults Discard Changes Save Changes Description Exit after writing all modified Setup item values to NVRAM. Exit leaving NVRAM unmodified. User is prompted if any of the setup fields were modified. Load default values for all SETUP items. Read previous values of all Setup items from NVRAM. Write all Setup item values to NVRAM.

4.3

CMOS Memory Definition

Only the BIOS needs to know the CMOS map. The CMOS map is not defined in the BIOS EPS. The CMOS map is available in the NVRAM.LST file generated for every BIOS release. The CMOS map is subject to change without notice.

4.4

CMOS Default Override

The BIOS detects the state of the CMOS default switch. If the switch is set to "CMOS Clear" prior to power-on or a hard reset, the BIOS changes the CMOS and NVRAM settings to a default state. This guarantees the system's ability to boot from floppy. Password settings are not affected by CMOS clear. The BIOS clears the ESCD parameter block and loads a null ESCD image. The boot order information is also cleared when CMOS is cleared via jumper. The configuration data for the on-board SCSI controllers is not cleared during a clear CMOS event as each device controls its own default settings If the Reset Configuration Data option is enabled in Setup, ESCD data and BIOS Boot specification data is cleared and reinitialized in next boot.

4.5

Flash Update Utility

The BIOS update utility (Phoenix* Phlash.exe) loads a fresh copy of the BIOS into flash ROM. The loaded code and data include the following:
· · · ·

On-board video BIOS, network controller BIOS, and SCSI BIOS. BIOS Setup utility. User-definable flash area (user binary area). OEM logo (splash screen).

When running Phoenix* Phlash in interactive mode, the user may choose to update a particular flash area. Updating a flash area takes a file or series of files from a hard or floppy disk, and loads it in the specified area of flash ROM. Note: The Phoenix Phlash utility must be run without the presence of a 386 protected mode control program, such as Windows* or EMM386*. Phoenix* Phlash uses the processor's flat addressing mode to update the flash part.

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4.5.1

Loading the System BIOS

The BIOS update utility (PHLASH) loads a new copy of the BIOS into Flash ROM. The loaded code and data include the following:
· · ·

On-board Video BIOS and SCSI BIOS BIOS Setup Utility Quiet Boot Logo Area

When running PHLASH in interactive mode, the user may choose to update a particular Flash area. Updating a flash area loads a file or a series of files from a hard or floppy disk into the specified area of Flash ROM. To manually load a portion of the BIOS, the user must specify which data file(s) to load. The choices include
· · · · ·

PLATCBLU.BIN PLATCXLU.BIN PLATCXXX.BIN PLATCXLX.BIN PLATCXXU.BIN

The last three letters specify the functions to perform during the flas h process:
· · · · ·

C B L U X

= = = = =

Rewrite BIOS Rewrite Bootblock Clear LOGO area Clear user binary place hold

This file is loaded into the PHLASH program with the /b=. The disk created by the BIOS.EXE program will automatic ally run phlash /s /b=PLATCXLU.BIN command in non-interactive mode. For a complete list of phlash switches, run phlash /h. Once an update of the system BIOS is complete, the user is prompted for a reboot. The user binary area is also updated during a system BIOS update. User binary can be updated independently of the system BIOS. CMOS is cleared when the system BIOS is updated.

4.5.2

OEM Customization

An OEM can customize the STL2 BIOS for product differentiation. The extent of customization is limited to what is stated in this section. OEMs can change the BIOS look and feel by adding their own splash screen/logo. OEMs can manage OEM-specific hardware, if any, by executing their own code during POST by using the "User-supplied BIOS Code Support."

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4.5.2.1

User-supplied BIOS Code Support

A 16 KB region of flash ROM is available to store a user binary. The Phoenix* Phlash utility allows the OEM or end user to update the user binary region with OEM supplied code and/or data. At several points throughout POST, control is passed to this user binary. Intel provides tools and reference code to help OEMs create a user binary. The user binary must adhere to the following requirements:
· ·

To allow detection by BIOS and protection from run time memory managers, the user binary must have an option ROM header (i.e., 55AAh, size). The system BIOS performs a scan of the user binary area at predefined points during POST. Mask bits must be set within the user binary to inform the BIOS which entry points exist. The system state must be preserved by the user binary (all registers, including extended and MMX, stack contents, and nonuser binary data space, etc.). The user binary code must be relocatable. The user binary is located within the first 1 MB of memory. The user binary code must not make any assumptions about the value of the code segment. The user binary code is always executed from RAM and never from flash. The user binary must not hook critical interrupts, must not reprogram the chip set, and must not take any action that affects the correct functioning of the system BIOS. The user binary ROM must be checksummed. The checksum byte must be placed in the last byte position of the 16K ROM.

· ·

· · ·

The BIOS copies the user binary into system memory before the first scan point. If the user binary reports that it does not contain run time code, it is located in conventional memory (0-640 KB). Reporting that the user binary has no run time code has the advantage of not using limited option ROM space (therefore, more option ROMs may be executed in a large system configuration). If user binary code is required at run time, it is copied into and executed from option ROM space (0C8000H ­ 0E7fffH). At each scan-point during POST, the system BIOS determines if the scan-point has a corresponding user binary entry point to transfer control to the user binary. Presence of a valid entry point in the user binary is determined by examining the bitmap at byte 4 of the user binary header; each entry point has a corresponding "presence" bit in this bitmap. If the bitmap has the appropriate bit set, an entry point ID is placed in the "AL" register and execution is passed to the address computed by (ADR(Byte 5)+5*scan sequence #). During execution, the user binary may access 11 bytes of extended BIOS data area RAM (EBDA). The segment of EBDA can be found at address 40:0e. Offset 18h through offset 22h is available for the user binary. The BIOS also reserves eight CMOS bits for the user binary. These bits are in an unchecksummed region of CMOS with default values of zero, and will always be located in the first bank of CMOS. These bits are contiguous, but are not in a fixed location. Upon entry into the user binary, DX contains a `token' that points to the reserved bits. This token is of the following format:

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MSB 15 # of bit available ­1 12 11 Bit offset from start of CMOS of first bit

LSB 0

The most significant four bits are equal to the number of CMOS bits available minus one. This field is equal to seven, since eight CMOS bits are available. The 12 least significant bits define the position of the CMOS bit in the real-time clock (RTC). This is a bit address rather than a byte address. The CMOS byte location is 1/8th of the 12-bit number, and the remainder is the starting bit position within that byte. For example, if the 12-bit number is 0109h, user binary can use bit 1 of CMOS byte 0108h/8 or 021h. It should be noted that the bits available to the user binary may span more than one byte of CMOS (i.e., a value of 07084h indicates that the upper nibble of byte 10h and the lower nibble of byte 11h are reserved for the user binary). The following code fragment shows the header and format for a user binary:
db MyCode PROC db db 55h, 0AAh, 20h FAR CBh 04h ; 16KB USER Area ; MUST be a FAR procedure ; Far return instruction ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bit map to define call points, a 1 in any bit specifies that the BIOS is called at that scan point in POST First transfer address used to point to user binary extension structure Word Pointer to extension structure Reserved This is a list of 7 transfer addresses, one for each bit in the bitmap. 5 Bytes must be used for each JMP to maintain proper offset for each entry. Unused entry JMP's should be filled with 5 byte filler or JMP to a RETF

db

CBh

dw dw JMP JMP JMP

? 0 ErrRet ErrRet Start

JMP JMP JMP JMP

ErrRet ErrRet ErrRet ErrRet

4.5.2.2

Scan Point Definitions

The table below defines the bitmap for each scan point, indicating when the scan point occurs and which resources are available (RAM, stack, binary data area, video, and keyboard).
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Table 4-21. User Binary Area Scan Point Definitions
Scan Point Near pointer to the user binary extension structure, mask bit is 0 if this structure is not present. Instead of a jump instruction the scan address (offset 5) contains an 0CB followed by a near pointer. Obsolete. No action taken. This scan occurs immediately after video initialization. This scan occurs immediately before video initialization. This scan occurs on POST error. On entry, BX contains the number of the POST error. This final scan occurs immediately prior to the INT 19 for normal boot and allows one to completely circumvent the normal INT 19 boot if desired. This scan occurs immediately before the normal option ROM scan. This scan occurs immediately following the option ROM area scan. Mask 01h RAM/Stack/ Binary Data Area (BDA) Not applicable Video/Keyboard Not applicable

02h 04h 08h 10h 20h

NA Yes Yes Yes Yes

NA Yes No Yes Yes

40h 80h

Yes Yes

Yes Yes

Table 4-22. Format of the User Binary Information Structure
Offset 0 Bit Definition Bit 0 = 1 if mandatory user binary, 0 if not mandatory. If a us er binary is mandatory, it will always be executed. If a platform supports a disabling of the user binary scan through Setup, this bit will override Setup setting. Bit 1 - 1 if runtime presence required (other than SMM user binary portion, SMM user binary will always be present in runtime irrespective of setting of this bit). 0, if not required in runtime, and can be discarded at boot time. Bit 7:2 ­ reserved for future expansion. 1 - 0fh Reserved for future expansion.

If this structure is not present (bit 0 of the scan point structure is not set), the system BIOS assumes that the user binary is not mandatory (bit 0 in User Binary Information Structure assumed cleared), and it is required in run time (bit 1 in User Binary Information Structure assumed set). 4.5.2.3 OEM Splash Screen

A 128-KB region of Flash ROM is available to store the OEM logo in compressed format. The BIOS will contain the standard Intel logo. Using the Phoenix Phlash utility, this region can be updated with an OEM supplied logo image. The OEM logo must fit within 640 X 480 size. If an OEM logo is flashed into the system, it will override the built in Intel logo.
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Intel supplies utilities that will compress and convert a 16 color bitmap file into a logo file suitable for Phoenix8 Phlash.

4.5.3

Language Area

The system BIOS language area can be updated only by updating the entire BIOS. The STL2 platform supports English, Spanish, French, German, and Italian. Intel provides translations for all the strings in five languages. These languages are selectable using Setup.

4.5.4

Recovery Mode

In the case of a corrupt or an unsuccessful update of the system BIOS, the STL2 can boot in recovery mode. To place STL2 into recovery mode, move the boot option jumper (jumper block 1J15 pins 9-10) to the recovery boot position. By default and for normal operation, pins 9 and 10 are not jumpered. Recovery mode requires at least 8 MB of RAM in the first DIMM socket, and drive A: must be set up to support a 3.5-inch, 1.44-MB floppy drive. (Note: the system requires 64 MB to boot). This is the mode of last resort, used only when the main system BIOS will not come up. In rec overy mode operation, PHLASH (in non-interactive mode only) automatically updates only the main system BIOS. PHLASH senses that STL2 is in recovery mode and automatically attempts to update the system BIOS Before powering up the system, the user must obtain a bootable diskette that contains a copy of the BIOS recovery files. This is created by running the "crisdisk.bat" from the compressed recovery file distributed with the BIOS. Note: During recovery mode, video will not be initialized and many high-pitched beep tones will be heard. The entire process takes two to four minutes. When the process is completed, the tones will stop. The user may see a "Checksum error" on the first boot after updating the BIOS. This is normal and should correct itself after the first boot. If a failure occurs, it is most likely that of the system BIOS .ROM file is corrupt or missing. After a successful update, power down the system and remove the jumper from pins 9-10. Power up the system. Verify that the BIOS version number matches the version of the entire BIOS used in the original attempt to update.

4.6

Error Messages and Error Codes

The system BIOS displays error messages on the video s creen. Prior to video initialization, beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS displays POST error codes on the video monitor. Following are definitions of POST error codes, POST beep codes, and system error messages.

4.6.1

POST Codes

After the video adapter has been successfully initialized, the BIOS indicates the current testing phase during POST by writing a 2-digit hex code to I/O location 80h. If a Port-80h card (Postcard*) is installed, it displays this 2-digit code on a pair of hex display LEDs.
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Table 4-23. Port-80h Code Definition
Code CP Meaning Phoenix* check point (port-80) code

The table below contains the port-80 codes displayed during the boot process. A beep code is a series of individual beeps on the PC speaker, each of equal length. The following table describes the error conditions associated with each beep code and the corresponding POST checkpoint code as seen by a `port 80h' card. For example, if an error occurs at checkpoint 22h, a beep code of 1-3-1-1 is generated. The "-" means there is a pause between the sequence that delimits the sequence.

Some POST codes occur prior to the video display being initialized. To assist in determining the fault, a unique beep-code is derived from these checkpoints as follows:
· · ·

The 8-bit test point is broken down to four 2-bit groups. Each group is made one-based (1 through 4) One to four beeps are generated based on each group's 2-bit pattern.

Example: Checkpoint 04Bh will be broken down to: And the beep code will be: 01 00 10 11 2­1­3­4

Table 4-24. Standard BIOS Port-80 Codes
CP 02 04 06 08 09 0A 0B 0C 0E 0F 10 11 12 14 16 18 1 -2 -2 -3 Beeps Verify Real Mode Get Processor type Initialize system hardware Initialize chipset registers with initial POST values Set in POST flag Initialize Processor registers Enable Processor cache Initialize caches to initial POST values Initialize I/O Initialize the local bus IDE Initialize Power Management Load alternate registers with initial POST values Restore Processor control word during warm boot Initialize keyboard controller BIOS ROM checksum 8254 timer initialization Reason

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CP 1A 1C 20 22 24 28 2A 2C 32 34 35 36 37 38 39 3A 3C 3D 40 42 44 46 47 48 49 4A 4B 4C 4E 50 52 54 55 56 58 5A 5C 60 62 64 66

Beeps 8237 DMA controller initialization Reset Programmable Interrupt Controller 1 -3 -1 -1 1 -3 -1 -3 1 -3 -3 -1 Test DRAM refresh Test 8742 Keyb oard Controller Set ES segment register to 4 GB

Reason

Autosize DRAM, system BIOS stops execution here if the BIOS does not detect any usable memory DIMMs Clear 8 MB base RAM Base RAM failure, BIOS stops execution here if entire memory is bad Test Processor bus -clock frequency Test CMOS RAM Initialize alternate chipset registers Warm start shut down Reinitialize the chipset Shadow system BIOS ROM Reinitialize the cache Autosize cache Configure advanced chipset registers Load alternate registers with CMOS values Set Initial Processor speed new Initialize interrupt vectors Initialize BIOS interrupts

1 -3 -4 -1

2 -1 -2 -3

Check ROM copyright notice Initialize manager for PCI Option ROMs Check video configuration against CMOS Initialize PCI bus and devices Initialize all video adapters in system Display QuietBoot screen Shadow video BIOS ROM Display copyright notice Display Processor type and speed Test keyboard Set key click if enabled USB initialization Enable keyboard

2 -2 -3 -1

Test for unexpected interrupts Display prompt "Press F2 to enter SETUP" Test RAM between 512 and 640 k Test extended memory Test extended memory address lines Jump to UserPatch1 Configure advanced cache registers

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CP 68 6A 6B 6C 6E 70 72 74 76 7A 7C 7D 7E 82 85 86 88 8A 8C 90 91 92 93 94 95 96 98 9A 9C 9E A0 A2 A4 A8 AA AC AE B0 B2 B4 B5 B6 1

Beeps Enable external and processor caches Display external cache size Load custom defaults if required Display shadow message Display non-disposable segments Display error messages Check for configuration errors Test real-ti me clock Check for keyboard errors Test for key lock on Set up hardware interrupt vectors Intelligent system monitoring Test coprocessor if present Detect and install external RS232 ports Initialize PC-compatible PnP ISA devices Re-initialize on board I/O ports Initialize BIOS Data Area Initialize Extended BIOS Data Area Initialize floppy controller Initialize hard disk controller Initialize local bus hard disk controller Jump to UserPatch2 Build MPTABLE for multi -processor boards Disable A20 address line Install CD-ROM for boot Clear huge ES segment register 1 -2

Reason

Search for option ROMs. One long, two short beeps on checksum failure Shadow option ROMs Set up Power Management Enable hardware interrupts Set time of day Check key lock Initialize typematic rate Erase F2 prompt Scan for F2 key stroke Enter SETU P Clear in-POST flag Check for errors POST done ­ prepare to boot Operating System One short beep before boot Display MultiBoot menu Check password, password is checked before option ROM scan

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CP B7 B8 BC BE BF C0 C8 C9 DO D2 D4 D6 D8 DA DC

Beeps ACPI initialization Clear global descriptor table Clear parity checkers Clear screen (optional) Check virus and backup reminders Try to boot with INT 19 Forced shutdown Flash recovery Interrupt handler error Unknown interrupt error Pending interrupt error Initialize option ROM error Shutdown error Extended Block Move Shutdown 10 error

Reason

Table 4-25. Recovery BIOS Port-80 Codes
CP E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 Beeps Initialize chip set Initialize bridge Initialize processor Initialize timer Initialize system I/O Check forced recovery boot Validate checksum Go to BIOS Initialize processors Set 4 GB segment limits Perform platform initialization Initialize PIC and DMA Initialize memory type Initialize memory size Shadow boot block Test system memory Initialize interrupt services Initialize real time clock Initialize video Initialize beeper Reason

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CP F4 F5 F6 F7

Beeps Initialize boot Restore segment limits to 64 KB Boot mini DOS Boot full DOS

Reason

4.6.2

POST Error Codes and Messages

The following table defines POST error codes and their associated messages. The BIOS prompts the us er to press a key in case of a serious error. Some error messages are preceded by the string "Error" to highlight that the system might be malfunctioning. All POST errors and warnings are logged in the system event log unless it is full.
Table 4-26. POST Error Messages and Codes
Code 0200: 0210: 0211: 0212: 0213: 0220: 0230: 0231: 0232: 0233: 0234: 0235: 0250: 0251: 0252: 0260: 0270: 0271: 02B0: 02B2: 02D0: 0B00: 0B1B: 0B1C: Failure Fixed Disk Stuck Key Keyboard error Keyboard Controller Failed Keyboard locked­ Unlock key switch Monito r type does not match CMOS­ Run SETUP System RAM Failed at offset Shadow RAM Failed at offset Extend RAM Failed at address line Memory type mixing detected Single ­ bit ECC error Multiple- bit ECC error System battery is dead ­ Replace and run SETUP System CMOS checksum bad ­ Default configuration used Password checksum bad - Passwords cleared System timer error Real time clock error Check date and time setting Diskette drive A error Incorrect Drive A type ­ run SETUP System cache error ­ Cache disabled Rebooted during BIOS boot at Post Code PCI System Error on Bus/Device/Function PCI Parity Error in Bus/Device/Function PCI system error in Bus/device/Function PCI system error in Bus/device/Function Incorrect Drive A type Processor cache error System timer error RTC error RTC time setting error Error Message Failure Description hard disk error Keyboard connection error Keyboard failure Keyboard Controller Failed Keyboard locked Monitor type does not match CMOS System RAM error Offset address Shadow RAM Failed Offset address Extended RAM failed Offset address Memory type mixing detected Memory 1 bit error detected Memory multiple-bit error detected NVRAM battery dead CMOS checksum error

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Code 0B50: 0B51: 0B5F: 0B60: 0B61: 0B62: 0B63: 0B6F: 0B70: 0B71: 0B74: 0B75: 0B7C: 0B80: 0B81: 0B82: 0B83: 0B90: 0B91: 0B92:

Error Message CPU#1 with error taken offline CPU#2 with error taken offline Forced to use CPU with error DIMM group #1 has been disabled DIMM group #2 has been disabled DIMM group #3 has been disabled DIMM group #4 has been disabled DIMM group with error is enabled The error occurred during temperature sensor reading System temperature out of the range The error occurred during voltage sensor reading System voltage out of the range The error occurred during redundant power module confirmation BMC Memory Test Failed BMC Firmware Code Area CRC check failed BMC core Hardware failure BMC IBF or OBF check failed BMC Platform Information Area corrupted. BMC update firmware corrupted. Internal Use Area of BMC FRU corrupted.

Failure Description Failed Processor#1 because an error was detected Failed Processor#2 because an error was detected An error detected in the entire processor Memory error, memory group #1 failed Memory error, memory group #2 failed Memory error, memory group #3 failed Memory error, memory group #4 failed An error detected in all the memory Error while d etecting a temperature failure. Temperature error detected. Error while detecting voltage System voltage error The error occurred while retrieving the power information BMC device (chip) failed

Access to BMC address failed BMC device(chip) failed SROM storing chassis information failed (Available for use except for FRU command and EMP function)

0B93: 0B94:

BMC SDR Repository empty. Intelligent Platform Management Bus (IPMB) signal lines do not respond. BMC FRU device failure.

BMC device (chip) failed SMC(Satellite Management Controller) failed (Available for use except for the access function to SMC via IPMB) SROM storing chassis information failed (Available for use except for FRU command and EMP function.)

0B95

0B96 0B97 0BB0: 0BB1: 0BD0: 0BD1: 0BD2: N/A N/A N/A N/A

BMC SDR Repository failure. BMC SEL device failure. SMBIOS ­ SROM data read error SMBIOS ­ SROM data checks um bad 1st SMBus device address not acknowledged. 1st SMBus device Error detected. 1st SMBus timeout. Expansion ROM not initialized. Invalid System Configuration Data System Configuration Data Read Error Resource Conflict

BMC device (chip) failed SROM data read error Bad checksum of SROM data Some SMBus device (chip) failed

PCI Expansion ROM card not initialized System configuration data destroyed System configuration data read error PCI card resource is not mapped correctly.

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Code N/A N/A 8503:

Error Message System Configuration Data Write error Warning: IRQ not configured Incorrect memory speed in location: XX, XX, ...

Failure Description System configuration data write error PCI interrupt is not configured correctly. Non-PC133 DIMMs have been installed in slots XX, XX, ...

A beep code is a series of individual beeps on the PC speaker, each of equal length. The following table describes the error conditions associated with each beep code and the corresponding POST check point code as seen by a port 80h card. For example, if an error occurs at checkpoint 22h, a beep code of 1-3-1-1 is generated. The beep codes 1-1-1-1, 1-5-11, 1-5-2-1 and 1-5-3-1 are reserved for BMC usage.
Table 4-27. POST Error Conditions and Beep Codes
Beeps 1 -2 -2 -3 1 -3 -1 -1 1 -3 -1 -3 1 -3 -3 -1 Error ROM Checksum Error DRAM Refresh Test Error Keyboard Controller Test Error Memory Not Detected Memory Capacity Check Error 1 -3 -4 -1 1 -3 -4 -3 1 -4 -1 -1 1 -4 -3 -3 2 -1 -2 -3 2 -2 -3 -1 2 -3 -1 -3 3 -3 -1 -4 1 -2 1 -2 1 -2 DRAM Address Test Error DRAM Test low byte Error DRAM Test high byte Error All Memory Group Errors BIOS ROM Copy-Write Test Error Unexpected Interrupt Test Error All Memory Group Errors Memory Not Detected Option ROM Initialization Error Video configuration fails OPTION ROM Checksum Error -- -- -- No memory. Can n ot write to memory No memory. Can not write to memory Memory address signal failure Memory data signal failure (low) Memory data signal failure (high) -- Error with Shadow RAM Unexpected interrupt Memory address signal failure -- Failure to initialize Option ROM BIOS Failure to initialize VGA BIOS Failure to initialize Option BIOS Cause Recommended Action Change system board Change memory DIMM' s Change system board Verify DIMM installation. Change memory DIMM' s Verify DIMM installation. Change memory DIMM' s Change DIMM or M/B Change DIMM or M/B Change DIMM or M/B -- Change system board Change CPU or system board Change DIMM or M/B -- Change system board or option board Change option video board or system board Change M/B or option board

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4.7

Identifying BIOS and BMC Revision Levels

The following sections provide information to help identify a system's current BIOS and BMC revision levels.

4.7.1

BIOS Revision Level Identification

During system POST, which runs automatically when the system is powered on, the monitor displays several messages, one of which identifies the BIOS revision level currently loaded on the system (see the following example). Phoenix BIOS 4.0 Release 6.0.250A In the example above, BIOS 6.0.250A is the current BIOS revision level loaded on the system. Note : Press the Esc key to see the diagnostic messages. Note: The BIOS Revision Level stated in the example might not reflect the actual BIOS setting in any particular system.

4.7.2

BMC Revision Level Identification

During system POST, which runs automatically when the system is powered on, system diagnostics are run. Following the memory test diagnostic, several messages appear to inform the user that the mouse was detected and system configuration data updated. The BMC messages follow these. To identify the system's current BMC revision level, see the following example. Base Board Management Controller Device ID :01 Device Revision :00 IPMI Version :1.0 Firmware Revision Self Test Result :

:00.60

In the example above, Firmware Revision 00.60 is the current BMC revision level loaded on the system. Note: Press the Esc key to see the diagnostic messages. Note: The Firmware Revision level in the example might not reflect the actual BMC revision level in any particular system.

4.8

Adaptec SCSI Utility

The Adaptec SCSI Utility detects the SCSI host adapters on the server board. The Adaptec SCSI Utility is used to:
· ·

Change default values Check and/or change SCSI device settings that may conflict with those of other devices in the server.
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4.8.1

Running the SCSI Utility

The user can access the Adaptec SCSI Utility when the system is powered on or rebooted. To run the Adaptec SCSI utility, perform the following procedure. 1. Power-on or reboot the system. 2. At the message to "Press Ctrl-A to run SCSI Utility", press Ctrl+A. 3. Choose the host adapter that needs to be configured. 4. The SCSI utility starts. When the Adaptec SCSI Utility detects more than one AIC -78xx host adapter, it displays a selection menu listing the bus and device number of each adapter. When the selection menu appears, select the channel that should be configured as follows.
Table 4-28. Channel Configuration
Bus: Device: Channel 01: 04: A 01: 04: B Note: 1. Internal SCSI Connector
1

Selected SCSI Adapter AIC*7899 AIC7899

When the adapter is selected, the following options display.
Table 4-29. Adapter Selection Options
Menu Configure/View Host Adapter Settings SCSI Disk Utilities Description Configure host adapter and device settings. The utility scans the SCSI bus for SCSI devices and reports a description of each device. Run these utilities before configuring SCSI devices.

To format a disk, verify disk media, or display a list of devices and their SCSI IDs, select "SCSI Disk Utilities". To configure the adapter or a device, select "Configure/View Host Adapter Settings."

4.8.2

Adaptec SCSI Utility Configuration Settings

The following keys are active for all Adaptec SCSI Utility screens.
Table 4-30. Active Keys for SCSI Utility Screens

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Key Arrows ENTER ESC F5 F6

Action Up and down arrows move from one parameter to another within a screen. Displays options for a configurable parameter. Selects an option. Moves back to previous screen or parameter or EXIT if at the Main menu. Switches between color and monochrome. Resets to host adapter defaults.

The following table shows the normal settings for the Adaptec SCSI Utility and provides a place to record any changes made to these settings.
Table 4-31. Adaptec SCSI Utility Setup Configurations
Option SCSI Bus Interface Definitions Host Adapter SCSI ID SCSI Parity Checking Host Adapter SCSI Termination Additional Options Boot D evice Options Boot Channel Boot SCSI ID Boot Logical Unit Number (LUN) Number SCSI Device Configuration Sync Transfer Rate (MBps) Initiate Wide Negotiation Enable Disconnection Send Start Unit Command Enable Write Back Cache BIOS Multiple LUN Support Include in BIOS Scan Advanced Configuration Options Plug-and-Play SCAM Support Reset SCSI Bus at IC Initialization Display Messages During BIOS Initialization Extended BIOS Translation for DOS Drives >1 Gbyte Verbose/Silent Mode Host Adapter BIOS (Configuration Utility Reserves BIOS Space) Domain Validation Support Removable Disks Under BIOS as Fixed Disks BIOS Support for Int13 Extensions Press Enter for menu A First 0 0 Press Enter for menu 160 Yes Yes Yes No No
1 1

Recommended Setting or Display Only 7 Enabled Enabled

User Setting

Yes

Press Enter for menu. Disabled Enabled Enabled Enabled Verbose Enabled Enabled Disabled Enabled
1, 2 1 1

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Notes: 1. 2. No effect if BIOS is disabled. Do not remove media from a removable media drive if it is under BIOS control.

4.8.3

Exiting Adaptec SCSI Utility

To exit the Adaptec SCSI Utility, the user presses the Esc key several times, until a message prompts him / her to exit. If changes have been made, the user is prompted to save them before exiting.

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Jumpers and Connectors

5.
5.1

Jumpers and Connectors
STL2 Server Board Jumper and Connector Locations

The following figure shows the location of the jumper blocks and connectors on the STL2 Server board.

Figure 5-1. STL2 Server Board Jumper and Connector Locations

Jumper and connector location key for Figure 5-1:
A. B. Main power connector (P33) VRM socket (P32)

C. Auxiliary power connector (P34) D. Primary processor (P13) E. F. Secondary processor (P14) Secondary processor heatsink fan connector (P36)

G. Power supply signal connector (P37) H. DIMM slots (P15-P18) I. J. IDE connector (P19) Floppy drive connector (P20)

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K. L.

Two pin speaker connector (P31) System fan connector FAN3A (P29)

M. Battery N. System fan connector FAN2A (P27) O. Front panel connector(P23) P. Four pin speaker connector (P25) Q. Ultra Single Ended (SE) SCSI connector (P9) R. Ultra160 LVD SCSI connector (P8) S. T. V. X. Y. Z. Configuration jumper block (1L4) Configuration jumper block (1J15) 33-MHz/32-bit PCI connectors Chassis intrusion connector (pins 1 -2 of 6A) System fan connector FAN1 (P11) I/O ports

U. CPU speed jumper block (5E1) W. 66-MHz/64-bit PCI connectors

AA. Primary processor heatsink fan connector (P12)

The following diagram shows the location of the connectors on the STL2 server board I/O panel.

Figure 5-2. I/O Back Panel Connectors

I/O Back Panel location key for Figure 5-1:
A. B. USB connectors Serial port 2 connector

C. Serial port 1 connector

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D. NMI switch E. F. Parallel port connector Keyboard connector

G. Mouse connector H. Video connector I. Network connector

5.2

Jumper Blocks

Jumpers on several jumper blocks of the STL2 server board are used to set the system configuration. The jumpers are small plastic -encased conductors (shorting plugs) that slip over two jumper pins on a jumper block. On the STL2 server board, the following jumper blocks are user-configurable. The figure below shows the default settings for the STL2 jumper blocks.
· · · ·

1J15 (CMOS and Password Clear) 5E1 (Processor Frequency) 1L4 (Configuration) 6A (Chassis Intrusion)
7 5 3 1 1 3 5 7 8 9
CMOS / Password Clear (Location 1J15)

Chassis Intrusion 8 (Location 6A)

6

2

4

6

8

10

12

4 2
CPU Clock Frequency (Location 5E1)

2

4

6

8

10

12

Configuration Jumper (Location 1L4)

2

4

6

8

10

12

1

3

5

7

9

11

1

3

5

7

9

11

Figure 5-3. STL2 Jumper Locations

5.2.1

Setting CMOS /Password Clear Jumper Block 1J15

Setting a jumper on system board jumper block 1J15 enables the user to clear the CMOS or to clear a forgotten password. See the above figure for the location of the jumper block location. The following table lists the factory default settings for jumper block 1J15, which are indicated in bold typeface. Procedures for setting the jumper on the block follow the table.
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Table 5-1. Jumper Block 1J15 Settings
Jumper Pin Numbers 1-2 3-4 5-6 7-8 9 - 10 Function CMOS clear Password protected Reserved Reserved BIOS Recovery Boot Jumper Position Open, Protect Closed, Erase Open, Normal Closed, Disable Open, Not Used Open, Not Used Open, Normal Closed, Recovery Boot What it does at system reset Preserves the contents of CMOS Clears CMOS Preserves the password Disables the password No function No function BIOS Recovery Boot disabled. Normal operation. If this jumper is set, BIOS recovery will be attempted from a bootable BIOS recovery floppy diskette. Provides a spare jumper

11 - 12

Spare

Closed, Spare

5.2.1.1

Clearing and Changing a Password

Clear and change a password as follows. 1. Power off the system, unplug the power cord, and remove the chassis panel. 2. Use needle nose pliers or your fingers to remove the spare jumper from pins 11-12 on jumper block 1J15. 3. Reinstall the jumper on pins 3-4 (Password Disable) of jumper block 1J15. 4. Reinstall the chassis panel, plug in the power cord(s), and power on the system. 5. While waiting for POST to complete, press the F2 key to enter BIOS setup. 6. This automatically clears all passwords, provided you save and exit the BIOS setup. 7. Power off the system, unplug the power cord(s), and remove the chassis panel. 8. Remove the Password Disable jumper from pins 3-4 and store the jumper on pins 11-12. 9. Replace the chassis panel, plug in the power cord(s), and power on the system. 10. To specify a new password run the BIOS Setup Utility as described earlier in this section. 5.2.1.2 Clearing CMOS

Clear CMOS as follows. 1. Power off the system, unplug the power cord, and remove the chassis panel. 2. Use needle-nose pliers or your fingers to remove the spare jumper from pins 11-12 on jumper block 1J15. 3. Position the jumper over pins 1-2 on jumper block 1J15. 4. Replace the chassis panel, plug in the power cable(s), and power on the system.
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5. After POST completes, power down the system, unplug the power cable(s), and remove the chassis panel. 6. Remove the jumper from pins 1-2 and store the jumper on pins 11-12. 7. Replace the chassis panel and connect system cables. 8. Power on the system, press F2 at the prompt to run the BIOS Setup utility, and select "Get Default Values" at the Exit menu. 5.2.1.3 Perfoming a BIOS Recovery Boot

In the event of BIOS corruption, the following procedure may be used to perform a BIOS Recovery. 1. Obtain the BIOS update file package from Intel's iBL or http://support.intel.com web site. 2. A file called "crisis.zip" is one of the files included with each STL2 BIOS release file package. Unzip the "crisis.zip" file to a directory on your hard drive. 3. Obtain a blank formatted floppy diskette (the floppy diskette should not be a bootable DOS diskette). Insert the blank formatted floppy diskette in the floppy drive. 4. From the MS -DOS prompt on an MS -DOS system, run the "crisdisk.bat" file from the directory you created on your hard drive. Follow the instructions on the screen to create the BIOS recovery floppy diskette. Note: The BIOS recovery floppy diskette will not be created correctly under the MS -DOS prompt window of a W indows operating system. It is necessary to use a MS -DOS system to create the BIOS recovery floppy diskette. 5. Power off the STL2 system, unplug the power cord, and remove the chassis panel. 6. Remove the spare jumper from pins 11-12 on jumper block 1J15. 7. Reinstall the jumper on pins 9-10 (BIOS Recovery) of jumper block 1J15. 8. Insert the BIOS recovery floppy diskette into the diskette drive. 9. Reinstall the chassis panel, plug in the power cord(s), and power on the system. 10. The screen will remain blank while the BIOS Recovery is performed. A number of beeps will occur during the BIOS update. The floppy drive access light will not turn off when the BIOS recovery is completed. Al low four minutes for the BIOS recovery to complete. If a POST card is installed in a PCI slot during the BIOS recovery, you can tell that the BIOS recovery is complete when code "EC" is displayed. When the BIOS Recovery is complete, it is safe to power off the system. 11. Power off the system, unplug the power cord(s), and remove the chassis panel. 12. Remove the BIOS Recovery jumper from pins 9-10 and store the jumper on pins 11-12. 13. Replace the chassis panel, plug in the power cord(s), and power on the system. 14. Perform a CMOS clear following the BIOS recovery. 5.2.1.4 Setting Processor Frequency Jumper Block 5E1

The jumpers on block 5E1 set the processor speed for the installed processor(s). The following table lists the settings for jumper block 5E1. Procedures for setting the jumpers follow the table.

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NOTE: It is not necessary to set the jumpers on the processor frequency jumper block 5E1 when using production level (SL Spec) processors. The server board will automatically detect the frequency of production processors. Table 5-2. Jumper Block 5E1 Settings
Processor Frequency ( MHz) 1 -2 667 733 800 867 933 1000 Not Jumpered Not Jumpered Jumpered Jumpered Jumpered Jumpered Jumper Settings 3 -4 Not Jumpered Not Jumpered Jumpered Jumpered Not Jumpered Not Jumpered 5 -6 Jumpered Jumpered Not Jumpered Not Jumpered Not Jumpered Not Jumpered 7 -8 Jumpered Not Jumpered Jumpered Not Jumpered Jumpered Not Jumpered

Set the processor frequency jumpers as follows. 1. Power off the system, unplug the power cord. 2. From the "Jumper Block 5E1 Settings" table, select the processor frequency matching the installed processor. 3. Move the jumpers to the settings shown in the "Jumper Block 5E1 Settings" table. 4. Reinstall the left panel, plug in the power c ord(s), and power on the system. The following table lists the factory default settings for jumper block 5E1, which are indicated in bold typeface.
Table 5-3. Jumper Block 1J15 Default Settings
Jumper Pin Numbers 1-2 3-4 5-6 7-8 9 - 10 11 - 12 Function Processor Frequency Select Processor Frequency Select Processor Frequency Select Processor Frequency Select 133-MHz FSB Spread Spectrum Jumper Position Open Open Open Open Open, Enabled Closed, Disabled Open, Disabled Closed, Enabled Enables 133 -MHz FSB Disables 133 -MHz FSB Disables FCC (Spread Spectrum) Enables FCC (Spread Spectrum) What it does at system reset

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5.2.2

Setting Configuration Jumper Block 1L4

Setting the jumpers on system board jumper block 1L4 enables the user to configure chassis intrusion sensors, or enable/disable BMC FRB (see the above figure for jumper block location). The following table lists the factory default settings for jumper block 1L4.
Table 5-4. Jumper Block 1L4 Settings
Jumper Pin Numbers 1­2 3­4 FRB Front Cover Chassis Intrusion Sensor Function Jumper Position Open, Enabled Closed, Disabled Open, Enabled Function Enables FRB Disables FRB Enables Chassis Intrusion sensing. This jumper may be used as a chassis intrusion switch connector. Disables Chassis I ntrusion sensing Enables Chassis Intrusion sensing No Function No Function No Functi on Provides a spare jumper

5­6

Side Cover Chassis Intrusion Sensor

Closed, Disabled Open, Enabled

7­8 9 ­ 10 11 ­ 12 9 ­ 11

No Function Reserved No Function Spare

Open, Not Used Open, Not Used Open, Not Used Closed, Spare

5.2.3

Setting Configuration Jumper Block 6A

Setting the jumpers on system board jumper block 6A enables the user to configure the front cover chassis intrusion sensing. Jumper 6A pins 1-2 may also be used as a chassis intrusion switch connector. The following table lists the factory default settings for jumper block 6A.
Table 5-5. Jumper Block 6A Settings
Jumper Pin Numbers 1­2 Function Front Cover Chassis Intrusion Sensor Jumper Position Open, Enabled Function Enables Chassis Intrusion sensing. This jumper may be used as a chassis intrusion switch connector. Disable s Chassis Intrusion sensing No Function No Function No Function

Closed, Disabled 3­4 5­6 7­8 Reserved No Function Reserved Open, Not Used Open, Not Used Open, Not Used

5.3

Connectors

This section provides pin information about the connectors on the STL2 server board.
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5.3.1

Main ATX Power Connector (P33)
Table 5-6. Main ATX Power Connector Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal +3.3 VDC +3.3 VDC COM +5 VDC COM +5 VDC COM PWR -GD 5 VSB +12 VDC +12 VDC +3.3 VDC Wire color Orange Orange Black Red Black Red Black Grey Purple Yellow Yellow Orange Pin 13 14 15 16 17 18 19 20 21 22 23 24 Signal +3.3 VDC -12 VDC COM PS-ON_L COM COM COM N.C. +5 VDC +5 VDC +5 VDC COM Wire Color Orange Blue Black Green Black Black Black N.C. Red Red Red Black

5.3.2

Auxilary ATX Power Connector (P34)
Table 5-7. Auxiliary ATX Power Connector Pinout
Pin 1 2 3 4 5 6 Signal +5 VDC +3.3 VDC +3.3 VDC COM COM COM Wire Color Red Orange Orange Black Black Black

5.3.3

I2C Power Connector (P37)
Table 5-8. I2C Power Connector Pinout
Pin 1 2 3 4 5 Signal N.C. N.C. +3.3 VDC N.C. N.C. Pin 6 7 8 9 10 Signal N.C. N.C. N.C. I2C Data I2C Clock

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5.3.4
· · ·

System Fan Connectors (P29, P27, P11)
System Fan 1: P11 System Fan 2: P27 System Fan 3: P29
Table 5-9. Board Fan Connector Pinout
Pin 1 2 3 Signal Fan Sense + 12 VDC COM

5.3.5
· ·

Processor Connectors (P12, P36)
Primary Processor Fan 1: P36 Secondary Processor Fan 2: P12
Table 5-10. Processor Fan Connector Pinout
Pin 1 2 3 Signal N.C. + 12 VDC COM

5.3.6

Speaker Connector (P31)
Table 5-11. Speaker Connector Pinout
Pin 1 2 Signal SPEAKER GND

5.3.7

Speaker Connector (P25)
Table 5-12. Speaker Connector Pinout
Pin 1 2 3 Signal SPEAKER GND N.C.

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4

GND

5.3.8

Diskette Drive Connecto r (P20)
18 34

1

17

Figure 5-4. Diskette Drive Connector Pin Diagram

Table 5-13. Diskette Drive Connector Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal FD_DENSEL No Connection FD_MDAID FD_INDEX_L FD_MON0_L FD_SEL1_L FD_SEL0_L FD_MON1_L FD_DIR_L FD_STEP_L FD_WDATA_L FD_WGATE_L FD_TRK0_L FD_WPT_L FD_RDATA_L FD_SIDE_L FD_DCHG_L

5.3.9

SVGA Video Port
Table 5-14. Video Port Connector Pinout
Pin 1 Signal Red Pin 9 Signal NC

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Pin 2 3 4 5 6 7 8

Signal Green Blue NC GND GND GND GND

Pin 10 11 12 13 14 15

Signal GND NC DDCDAT HSYNC VSYNC DDCCLK

5.3.10

Keyboard and Mouse Connectors

The keyboard and mouse connectors are functionally equivalent.
Table 5-15. Keyboard and Mouse Connector Pinouts
Pin 1 2 3 4 5 6 Keyboard Signal KEYDAT GND GND FUSED_VCC (+5 V) KEYCLK NC Pin 1 2 3 4 5 6 NC GND FUSED_VCC (+5 V) MSECLK NC Mouse Signal MSEDAT

5.3.11

Parallel Port
Table 5-16. Parallel Port Connector Pinouts
Pin 1 2 3 4 5 6 7 8 9 Signal STROBE_L Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Pin 10 11 12 13 14 15 16 17 18- 25 Signal ACK_L Busy PE SLCT AUTO_L ERROR_L INIT_L SLCTIN_L GND

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5.3.12

Serial Ports COM1 and COM2
Table 5-17. Serial Ports COM1 and COM2 Connector Pinouts
Pin 1 2 3 4 5 6 7 8 9 Signal DCD RXD TXD DTR GND DSR RTS CTS RIA Description Data carrier detected Receive data Transmit data Data terminal ready Ground Data set ready Return to send Clear to send Ring indication active

5.3.13

RJ-45 LAN Connector
Table 5-18. RJ-45 LAN Connector Signals

Pin 1 2 3 4 5 6 7 8 TX+ TXRX+ NC NC RXNC NC

Signal

Description Transmit data plus --the positive signal for the TD differential pair contains the serial output data stream transmitted onto the network Transmit data m inus --the negative signal for the TD differential pair contains the same output as pin 1 Receive data plus --the positive signal for the RD differential pair contains the serial input data stream received from the network

Receive d ata minus --the negative signal for the RD differential pair contains the same input as pin 3

5.3.14

USB Connectors
Table 5-19. USB Connectors
USB 1 Pin 1 2 3 4 Signal +5 VDC USB_P1_N USB_P1_P GND USB 2 Pin 1 2 3 4 Signal +5 VDC USB_P0_N USB_P0_P GND

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5.3.15

Ultra SCSI Connector (P9)
Table 5-20. Ultra SCSI Connector Pinout
Pin 1-16 17 18 19 20-34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Signal GND TERMPWR TERMPWR NC GND SCD12_L SCD13_L SCD14_L SCD15_L SCDPH_L SCD0_L SCD1_L SCD2_L SCD3_L SCD4_L SCD5_L SCD6_L SCD7_L SCDP_L Pin 49-50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal GND TERMPWR TERMPWR NC GND SATN_L GND SBSY_L SAC K_L RESET_L SMSG_L SSEL_L SCD_L SREQ_L SI/O_L SCD8_L SCD9_L SCD10_L SCD11_L

5.3.16

Ultra160 SCSI Connector (P8)
Table 5-21. Ultra160 SCSI Connector
Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal SCDAP12 SCDAP13 SCDAP14 SCDAP15 SCDAPHP SCDAP0 SCDAP1 SCDAP2 SCDAP3 SCDAP4 SCDAP5 SCDAP6 Pin 35 36 37 38 39 40 41 42 43 44 45 46 Signal SCDAN12_L SCDAN13_L SCDAN14_L SCDAN15_L SCDAPHN_L SCDAN0_L SCDAN1_L SCDAN2_L SCDAN3_L SCDAN4_L SCDAN5_L SCDAN6_L

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Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Signal SCDAP7 SCDAPLP GND DIFFSENSA TRMPWRA TRMPWRA No Connection GND ATNAP GND BSY ACK RSTAP MSGAP SELAP CDAP REQAP IOAP SCDAP8 SCDAP9 SCDAP10 SCDAP11

Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Signal SCDAN7_L SCDAPLN_L GND GND TRMPWRA TRMPWRA No Connection GND ATNAN_L GND BSYAN_L ACKAN_L RSTAN_L MSGAN_L SELAN_L CDAN_L REQAN_L IOAN_L SCDAN8_L SCDAN9_L SCDAN10_L SCDAN11_L

5.3.17

IDE Connector (P19)
21 40

1

20

Figure 5-5. IDE Connector Pin Diagram

If no IDE drives are present, no IDE cable should be connected. If a single IDE drive is installed, it must be connected at the end of the cable.
Table 5-22. IDE Connector Pinout
Pin 1 Signal RESET_L Pin 21 Signal GND

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Pin 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Signal DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 GND IDEDRQ DIOW_L DIOR_L IORDY IDEDAK_L IDEIRQ IDESA1 IDESA0 IDECS0_L Keyed

Pin 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DD8 DD9

Signal

DD10 DD11 DD12 DD13 DD14 DD15 No Connection GND GND GND GND GND No Connection No Connection IDESA2 IDECS1_L GND

5.3.18

32-Bit PCI Connector
Table 5-23. 32-Bit PCI Connector Pinout
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Signal TRST_L +12 V TMS TDI +5 V INTA_L INTC_L +5 V Reserved +5 V Reserved GND GND Reserved RST_L +5 V Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 Signal -12 V TCK GND TD0 (NC) +5 V +5 V INTB_L INTD_L PRSNT1_L Reserved PRSNT2_L GND GND Reserved GND PCICLK Pin A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 Signal AD16 +3.3 V FRAME_L GND TRDY_L GND STOP_L +3.3 V SDONE SBO_L GND PARITY AD15 +3.3 V AD13 AD11 Pin B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 Signal AD17 CBE2_L GND IRDY_L +3.3 V DEVSEL_L GND LOCK_L PERR_L +3.3 V SERR_L +3.3 V CBE1_L AD14 GND AD12

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A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

GNT_L GND PME_L AD30 +3.3 V AD28 AD26 GND AD24 IDSEL +3.3 V AD22 AD20 GND AD18

B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31

GND REQ_L +5 V AD31 AD29 GND AD27 AD25 +3.3 V CBE3_L AD23 GND AD21 AD19 +3.3 V

A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

GND AD9 KEY KEY CBE0_L +3.3 V AD6 AD4 GND AD2 AD0 +5 V REQ64_L +5 V +5 V

B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

AD10 GND KEY KEY AD8 AD7 +3.3 V AD5 AD3 GND AD1 +5 V ACK64_L +5 V +5 V

5.3.19

64-Bit PCI Connector
Table 5-24. 64-Bit PCI Connctor Pinout
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Signal TRST_L +12 V TMS TDI +5 V INTA_L INTC_L +5 V Reserved +5 V Reserved GND GND Reserved RST_L +5 V GNT_L GND PME_L AD30 +3.3 V Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 Signal -12 V TCK GND TD0 (NC) +5 V +5 V INTB_L INTD_L PRSNT1_L Reserved PRSNT2_L GND GND Reserved GND PCICLK GND REQ_L +5 V AD31 AD29 Pin A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 Signal GND AD9 KEY KEY CBE0_L +3.3 V AD6 AD4 GND AD2 AD0 +5 V REQ64_L +5 V +5 V GND CBE7_L CBE5_L +3.3 V Parity AD62 Pin B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 Signal AD10 M66EN KEY KEY AD8 AD7 +3.3 V AD5 AD3 GND AD1 +5 V ACK64_L +5 V +5 V Reserved GND CBE6_L CBE4_L GND AD63

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Pin A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47

Signal AD28 AD26 GND AD24 IDSEL +3.3 V AD22 AD20 GND AD18 AD16 +3.3 V FRAME_L GND TRDY_L GND STOP_L +3.3 V SDONE SBO_L GND PARITY AD15 +3.3 V AD13 AD11

Pin B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47

Signal GND AD27 AD25 +3.3 V CBE3_L AD23 GND AD21 AD19 +3.3 V AD17 CBE2_L GND IRDY_L +3.3 V DEVSEL_L GND LOCK_L PERR_L +3.3 V SERR_L +3.3 V CBE1_L AD14 GND AD12

Pin A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94

Signal GND AD60 AD58 GND AD56 AD54 +3.3 V AD52 AD50 GND AD48 AD46 GND AD44 AD42 +3.3 V AD40 AD38 GND AD36 AD34 GND AD32 Reserved GND Reserved

Pin B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94

Signal AD61 +3.3 V AD59 AD57 GND AD55 AD53 GND AD51 AD49 +3.3 V AD47 AD45 GND AD43 AD41 GND AD39 AD37 +3.3 V AD35 AD33 GND Reserved Reserved GND

5.3.20

Front Panel 24-pin Connector Pinout (P23)
Table 5-25. Front Panel 24-pin Connector Pinout
Pin 1 2 3 4 5 6 7 8 9 Reserved Key Fan Fault LED Anode Power LED Cathode Fan Fault LED Cathode Hard Drive Activity LED Anode Power Fault LED Anode Hard Drive Activity LED Cathode Description Power LED Anode

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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Power Fault LED Cathode Power Switch (Low True) NIC Acti vity LED Anode Power Switch (GND) NIC Activity LED Cathode Reset Switch (Low True) Reserved Reset Switch (GND) Reserved ACPI Sleep Switch (Low True) Chassis Intrusion ACPI Sleep Switch (GND) Reserved NMI to CPU Switch (Low True) Reserved

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Baseboard Specifications

6.

Baseboard Specifications

This chapter specifies the operational parameters and physical characteristics for the STL2 server board. This is a board-level specification only. System specifications are beyond the scope of this document.

6.1

Estimated Baseboard MTBF

The table below shows the estimated MT BF (Mean Time Between Failures) calculated numbers for the STL2 server board. No specific chassis was used for the calculation, although many of the line items listed are those used in the Intel® SR2050 server chassis.
Table 6-1. Estimated MTBF Calculated Numbers for STL2

Mean Time between Interrupts: 42,579 hours Maximum Operating Temperature: 35 °C
Duty Sub Sub Assy Sub Sub Assembly Description STL2 server board Front panel board Processor Processor terminator SCSI backplane board PCI Riser IDE CD- ROM Seagate Hard Drive PRO 100 NIC Power supply 1.44- MB, 3.5- inch FDU DIMM Fan Assy QTY 1 1 0 0 1 1 1 0 0 0 0 1 0 MTBF Quote (hrs) 298,000 11,734,747 1,000,000 13,819,790 248,836 7,644,250 75,000 1,000,000 464,382 100,000 81,000 1,358,496 612,184 Sub Assy Temp Quote (C) 25 25 55 25 25 25 25 55 55 50 35 55 40 Assy Duty Cycle Quote (%) 100 100 100 100 100 100 20 100 100 100 5 100 100 Cycle as used in Sys (%) 100 100 100 100 100 100 5 100 100 100 1 100 100 MTBF (in hours) Sub Assy temp in sys (C) 40 40 N/A N/A 40 46.9 36.3 N/A N/A N/A N/A 70 N/A Total Sub Assy MTBF (in hrs) 140,614 5,537,162 NA NA 117,416 2,608,324 169,338 NA NA NA NA 720,407 NA Total Sub Assy Failure Rate (FITs) 7,112 181 NA NA 8,517 383 5,905 NA NA NA NA 1,388 NA 23,486 42,579

Total Failure Rate (FITs)

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6.2

Absolute Maximum Ratings

Operation of the STL2 server board at conditions beyoond those shown in the following table may cause permanent damage to the system (provided for stress testing only). Exposure to absolute maximum rating conditions for extended periods may affect system reliability.
Table 6-2. Absolute Maximum Ratings
Operating Temperature Storage Temperature Voltage on any signal with respect to ground 3.3 -V Supply Voltage with Respect to ground 5-V Supply Voltage with Respect to ground 0 °C to +55 °C ** -55 °C to +150 °C -0.3 V to VDD + 0.3 V *** -0.3 to +3.63 V -0.3 to +5.5 V

**Chassis design must provide proper airflow to avoid exceeding Pentium® III maximum case temperature. *** VDD means supply voltage for the device.

6.3

Calculated Power Consumption

The following table shows the calculated power consumption for each of the power supply voltage rails for the STL2 server board. These values were calculated using the specifications for the on-board components and processors. Assumptions for add-in card power and other peripherals powered from the server board are included in the table. Customers will need to modify the calculated power consumption numbers based on their anticipated usage ­ watts per PCI slot, etc.
NOTE: The following numbers are provided as an example. Actual power consumption will vary depending on the exact STL2 configuration. Refer to the appropriate system chassis document for more information. Table 6-3. STL2 Server Board Calculated Power Consumption
Device(s) Server Board Processors (87% VRM efficiency, 100% utilization) 1 x 667-MHz/256-K processor 1 x 733-MHz/256-K processor 1x 800EB-MHz/256-K processor 1x 866-MHz/256-K processor 4.02 A 4.21 A 4.78 A 5.26 A 3.3 V 4.6 A 12.5 A +5 V +12 V 0.06 A -12 V 0.0 A 5-V Standby 0.18 A Totals

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Baseboard Specifications

Device(s) 1x 933-MHz/256-K processor 1x 1 -GHz/256-K processor Memory (Four PC133 Registered GB SDRAM DIMMs) PCI Connectors 32-bit PCI slots (1 0W per slot on 5 V) 64-bit PCI slots (10 W per slot on 3.3 V) USB (500mA per connector) Keyboa rd/Mouse SCSI term power Fans (Three chassis and two processor) Total Current Total Power

3.3 V 5.63 A 6.0 A 5.5 A

+5 V

+12 V

-12 V

5-V Standby

Totals

8.0 A 6.06 A 1.00 A 0.50 A Included in board spec. 1.32 A 16.16 A 53.33 W 34.0 A 170.0 W 1.38 A 16.6 W 0.0 A 0.0 W

0.4 A 0.2 A

0.78 A 3.9 W

Total 243.83 W

The total power calculation assumes a system configuration containing dual Pentium® III 1-GHz processors with the VRM for both processors supplied by the 5-V source, four 1-GHz DIMMs, all PCI slots containing 10-W cards, two USB devices, keyboard and mouse, three chassis fans, and two processor fan heat sinks.

6.4

Measured Power Consumption

A STL2 FAB 2 server board was configured with dual 866-MHz processors, both supplied by the 5-V voltage regulation modules (VRMs), and four 1-GB PC133 SDRAM DIMMs (Infineon part number HYS72V128320GR). The system was configured with Microsoft Windows NT 4.0. Test software utilized during the power consumption measurement consisted of the Hipower test suite, used to simulate medium processor activity, and the WinMTA memory stress test suite, used to simulate high memory activity. The STL2 server board measured power consumption including the memory and processor power is listed in the following table.
Table 6-4. STL2 Server Board Measured Power Consumption
Device(s) Server Board 3.3 V 6.0 A +5 V 8.5 A +12 V 0.01 A Total Wattage 63.5 W

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6.5

Mechanical Specifications

The diagram on the following page shows the mechanical specifications of the STL2 server board. All dimensions are in inches. Connectors are dimensioned to pin 1.

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Regulatory and Integration Information

7.
7.1

Regulatory and Integration Information
Regulatory Compliance

The STL2 server board complies with the following safety standard requirements.
Table 7-1. Safety Regulations
Regulation UL 1950/CSA950 EN 60950 IEC60 950 EMKO-TSE (74-SEC) 207/94 EU Low Voltage Directive 73/23/ECC Title Bi-National Standard for Safety of Information Technology Equipment including Electrical Business Equipment. (USA and Canada) The Standard for Safety of Information Technology Equipment including Electrical Business Equipment. (European Community) The Standard for Safety of Information Technology Equipment including Electrical Bus iness Equipment. (International) Summary of Nordic deviations to EN 60950. (Norway, Sweden, Denmark, and Finland) Compliance to EU LV Directive via EN60 950 / IEC 60950

The STL2 server board has been tested and verified to comply with the following EMC regulations when installed in a compatible Intel host system. For information on Intel compatible host system(s), refer to Intel's Server Builder website, or contact your local Intel representative.
Table 7-2. EMC Regulations
Regulation FCC ­ Class A ICES-003 ­ Class A CISPR 22 VCCI ­ Class A EN55022 EN55024 EU EMC Directive 89/336/EEC BSMI (CNS13438) ­ Class A C-tick (AS/NZS 3548) Compliance to EU EMC Directive via EN55022 & EN55024 Taiwan EMC Regulations based on CISPR 22 Australia & New Zealand EMS Regulations based on CISPR 22 Title Title 47 of the Code of Federal Regulations, Parts 2 and 15, Subpart B, pertaining to unintentional radiators. (USA) Interference-Causing Equipment Standard, Digital Apparatus, Class A (including CRC c. 1374) (Canada). Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment. (International) Implementation Regulations for Voluntary Control of Radio Interference by Data Processing Equipment and Electronic Office Machines. (Japan) Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment. (Europe) Generic Immunity Standard; currently compliance is determined via testing to IEC 801-2, -3, and -4. (Europe)

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This server board assembly has the following required certification type markings:
· · · · · · ·

UL Joint Recognition Mark: Consists of small c (for Canada) followed by a stylized backward UR and followed by a small US (USA) (on component side). Intel's UL File Number E139761 (Component side). Battery "+" marking: located on the component side of the board in close proximity to the battery holder. CE Mark: (Component side) Australian C-Tick Mark: Consists of solid circle with white check mark and supplier code N232. Russian GOST (Open letter "C" with the letter "P" inside the "C" and the letter "T" in the mouth of the "C". Taiwan BSMI Certification mark. Two Chinese characters and an 8 digit number.

7.2

Installation Instructions

CAUTION: Follow these guidelines to meet safety and regulatory requirements when installing this board as sembly. Read and adhere to these instructions and to the instructions supplied with the host computer and associated modules. If the instructions for the host computer are inconsistent with these instructions or the instructions for associated modules, contact the supplier's technical support to find out how to ensure that the system meets safety and regulatory requirements. If the instructions are not followed, the user increases safety risk and the possibility of noncompliance with regional laws and regulations.

7.2.1

Ensure EMC

Before computer integration, the host chassis, power supply, and other modules should pass EMC certification testing. In the installation instructions for the host chassis, power supply, and other modules, pay close attention to the following:
· · · ·

Certifications. External I/O cable shielding and filtering. Mounting, grounding, and bonding requirements. Keying connectors when mismating of connectors could be hazardous.

If the host chassis, power supply, and other modules have not passed applic able EMC certification testing before integration, EMC testing must be conducted on a representative sample of the newly completed computer.

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7.2.2

Ensure Host Computer and Accessory Module Certifications

The host computer and any added subassembly (such as a board or drive assembly, including internal or external wiring) should be certified for the region(s) where the end product will be used. Marks on the product are proof of certification. Certification marks are as follows: 7.2.2.1 In Europe

The CE marking signifies compliance with all relevant European requirements. If the host computer does not bear the CE marking, obtain a supplier's Declaration of Conformity to the appropriate standards required by the European EMC Directive and Low Voltage Directive. Other directives, such as the Machinery and Telecommunications Directives, may also apply depending on the type of product. No regulatory assessment is necessary for low voltage DC wiring used internally or wiring used externally when provided with appropriate overcurrent protection. Appropriate protection is provided by a maximum 8 Amp current limiting circuit or a maximum 5-Amp fuse or positive temperature coefficient (PTC) resistor. This Intel server board has PTCs on all external ports that provide DC power externally. 7.2.2.2 In the United States

A certification mark by a Nationally Recognized Testing Laboratory (NRTL) such as UL, CSA, or ETL signifies compliance with safety requirements . External wiring must be UL Listed and suitable for the intended use. Internal wiring must be UL Listed or Recognized and rated for applicable voltages and temperatures. The FCC mark (Class A for commercial or industrial only or Class B for residential) s ignifies compliance with electromagnetic interference requirements. 7.2.2.3 In Canada

A nationally recognized certification mark such as CSA or cUL signifies compliance with safety requirements. No regulatory assessment is necessary for low voltage DC wiring used internally or wiring used externally when provided with appropriate overcurrent protection. Appropriate protection is provided by a maximum 8 Amp current limiting circuit or a maximum approved 5 Amp fuse or positive temperature coefficient (PTC) resistor. This server board has PTCs on all external ports that provide DC power externally.

7.2.3

Prevent Power Supply Overload

The power supply output must not be overloaded. To avoid overloading the power supply, the calculated total current load of all the modules within the computer should be less than the maximum output current rating of the power supply. If this is not adhered to, the power supply may overheat, catch fire, or damage the insulation that separates hazardous AC line circuitry from low voltage user accessible circuitry and result in a shock hazard. If the load drawn by a module cannot be determined by the markings and instructions supplied with the module, contact the module supplier's technical support.

7.2.4

Place Battery Marking on Computer

There is insufficient space on this server board to provide instructions for replacing and disposing of the battery. The following warning must be placed permanently and legibly on the host computer as near as possible to the battery.

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WARNING: Danger of explosion if battery is incorrectly replaced.
Replace with only the same or equivalent type recommended by the manufacturer. Dispose of used batteries according to the manufacturer's instructions.

7.2.5

Use Only for Intended Applications

This product was evaluated for use in ITE computers that will be installed in offices, schools, computer rooms and similar locations. The suitability of this product for other product categories other than ITE applications, (such as medical, industrial, alarm systems, and test equipment) may require further evaluation.

7.2.6

Installation Precautions

During the installation and testing of the board, the user should observe all warnings and cautions in the installation instructions. To avoid injury, be aware of the following:
· · · · · ·

Sharp pins on connectors. Sharp pins on printed circuit assemblies. Rough edges and sharp corners on the chassis. Hot components (like processors, voltage regulators, and heat sinks). Damage to wires that could cause a short circuit. Observe all warnings and cautions that instruct you to refer computer servicing to qualified technical personnel.

WARNING: Do not open the power supply. There is risk of electric shock and burns from high voltage and rapid overheating. Refer servicing of the power supply to qualified technical personnel.

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Errata Listing

8.
8.1

Errata Listing
Summary Errata Table

The following table indicates the errata that apply to the STL2 server board. This table uses the following notations:

8.1.1
Doc: Fix: Fixed: NoFix: NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Plans NoFix NoFix NoFix NoFix NoFix NoFix Fixed NoFix NoFix NoFix NoFix Fixed Fixed Fixed Fixed NoFix Fixed NoFix

Codes Used in Summary Table
Intel intends to update the appropriate documentation in a future re vision. This erratum is intended to be fixed in a future stepping of the component. This erratum has been previously fixed. There are no plans to fix this erratum. ERRATA Processor fan speeds cannot be monitored Full length PCI cards cannot be installed in PCI slot 1 Intrusion switch connector does not fit on connector 6A pins 1&2 in the SR2050 chassis Microsoft* Windows 98* will not install 4GB memory size reported incorrectly durin g POST Arrowhead card fails installation under Microsoft* Windows 2000* BIOS update process does not ask for confirmation BMC firmware update process power down the system automatically upon completion BMC firmware corru ption is a non-recoverable condition. STL2/SC5000 system exceeds system level acoustic specification PIO IDE mode 3 drives cause no boot condition SC5000 350 watt power supply fan failure not reported in the SEL Boot order issue with SCSI CDROM drives Three percent no boot failure following battery replacement due to Super I/O errata Red Hat Linux 6.1 installation issue SC5000/SR2050 chassis HSC firmware update is not possible with the STL2 server board installed Red Hat Linux 6.2 SBE2 and 7.0 only recognize 64MB of memory with BIOS Release 1.2 and 1.3 STL2 System Setup Utility does not allow display or modification of system IRQ mapping

8.2

Errata

1. Processor fan speeds cannot be monitored The STL2 server board was not designed to monitor the speed of either the primary or secondary processor fans. The tachometer signal (pin 1) on both processor fan connectors
PROBLEM:

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(P12 and P36) is not connected. Only the 12-V signal (pin 2) and ground signal (pin 3) are supplied to the processor fan connectors. The processor fan speed cannot be monitored through the ISC software. Processor fan failures will not be recorded in the system event log (SEL).
IMPLICATION :
ORKAROUND: The STL2 server board includes the ability to monitor the die temperature of the processor. The ISC version 2.5 software that ships with the STL2 server board includes the ability to monitor processor temperature. It is recommended that processor temperature be monitored in place of processor fan speed if processor monitoring is required.

W

STATUS:

NoFix.

2. Full length PCI cards cannot be installed in PCI slot 1 Full length PCI cards cannot be installed in PCI slot 1 of the STL2 server board, as a full length card will interfere with the DIMM slots.
PROBLEM: IMPLICATION : W

Full length PCI cards cannot be utilized in PCI slot 1 of the STL2 server board.
:

ORKAROUND

Install any full length PCI cards in PCI slot 2-6 of the STL2 server board.

STATUS:

NoFix. Intrusion switch connector does not fit on connector 6A pins 1&2 in the SR2050 chassis

3.

PROBLEM: When the STL2 server board is installed in the SR2000 chassis, the back side area for the PCI add

in cards is indented 5/16 inches. This indented area is directly over the STL2 connector 6A, where the chassis intrusion connector is located. This indented area does not touch the connector pins, but there is not enough clearance to attach any connectors to this site.
IMPLICATION : W

The SR2050 chassis intrusion s witch cannot be connected to STL2 connector 6A.
: The SR2050 chassis intrusion switch should be connected to STL2 jumper 1L4 pins 3-4.

ORKAROUND

STATUS:

NoFix. Microsoft* Windows 98* will not install

4.

PROBLEM: Microsoft* Windows 98* will not install the STL2 server board. Various error messages and hangs

have been encountered when attempting the installation.
IMPLICATION : W

Microsoft* Windows 98* cannot be utilized with the STL2 server board.
: No workaround exists for this issue.

ORKAROUND

STATUS:

NoFix. 4GB memory size reported incorrectly during POST

5.

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Errata Listing

PROBLEM: When 4 GB total memory is installed in the STL2 server board, the BIOS reports the extended

memory size as 3,999 MB during POST. The expected extended memory size is 4095 MB. The OS can access all of the installed memory.

The BIOS will report the extended memory size as 3,999 MB during POST when 4 GB total memory is installed in the STL2 server board. The OS can access all of the installed memory, so this issue has no impact on product functionality.
IMPLICATION : W
ORKAROUND

: No workaround exists for this issue.

NoFix. This issue is caused by an errata in the ServerWorks* III LE chipset. No fix is planned at this time.
STATUS:

6.

Arrowhead card fails installation under Microsoft* Windows 2000*

PROBLEM: The Arrowhead server management card will not complete installation when used with the STL2

server board and Microsoft* Windows 2000*. A black screen is encountered during installation.

The Arrowhead server management card cannot be utilized with the STL2 server board and Microsoft* Windows 2000*.
IMPLICATION : W
ORKAROUND

: No workaround exists for this issue.

STATUS:

NoFix. BIOS update process does not ask for confirmation

7.

PROBLEM: When a STL2 BIOS update is performed, the STL2 BIOS update utility immediately begins

programming the BIOS upon boot from the BIOS update diskette, without prompting for confirmation first. This is different than the BIOS update process for other Intel server products, which prompts the user to confirm the BIOS update before proceeding.

STL2 BIOS updates will be performed immediately after booting to the BIOS update diskette, without user confirmations.
IMPLICATION : W
ORKAROUND

: No workaround exists for this issue.

STATUS:

Fixed. This issue has been fixed in STL2 BIO S Release 1.2 (Build 16) and later versions. BMC firmware update process powers down the system automatically upon completion

8.

PROBLEM: When a STL2 BMC firmware update is performed, the STL2 BMC firmware update utility

automatically powers down the system upon successful completion, without prompting for power down confirmation first. This is different than the BMC firmware update process for other Intel server products.

The STL2 system will automatically power down when a BMC firmware update is successfully completed. This is expected behavior.
IMPLICATION : W
ORKAROUND

: No workaround exists for this issue.

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Fixed. STL2 BMC firmware update versions 1.17 and 11.17 and later versions include a user prompt that the system will power down after a key is pressed, instead of immediately powering down the system upon successful completion of the BMC firmware update.
STATUS:

9.

BMC firmware corruption is a non-recoverable condition

PROBLEM: If BMC firmware corruption occurs on a STL2 board during the BMC firmware update process or by

other means, this is a non-recoverable condition. This is different from some other Intel server boards which include a BMC force update jumper to allow recovery from BMC firmware corruption.

Since BMC firmware corruption is a non-recoverable condition, extra care should be taken to not accidentally power down the STL2 system when a BMC firmware update is in process.
IMPLICATION : W
ORKAROUND

: No workaround exists for this issue.

STATUS:

NoFix. STL2 / SC5000 system exceeds system level acoustic specification

10.

PROBLEM: Intel server boards typically have a protection circuit on the 12 V fan voltage pin that reduces the

fan voltage from 12 V to approximately 11 V. On the STL2 server board, there is no protection circuit on the fan voltage pin, so the full 12 V is supplied to the system fan. This causes the system fans to run faster than designed and pushes the system acoustic level over Intel's specified 50 dBA acoustic limit.

If the SC5000 chassis fans are connected directly to the STL2 baseboard fan connectors, the STL2/SC5000 system will exceed the acoustic level of 50 dB. This issue may affect customers using third party chassis.
IMPLICATION :
ORKAROUND: A fan extension cable with a 5 ohm resistor has been designed (Intel part number A38302001), which lowers the system fan voltage. Two fan extension cables are includes in the STL2 server boxed board. It is necessary to use a fan extension cable with each of the SC5000 system fans in order to lower the system level acoustics below 50 dBA. Customer using third party chassis should evaluate their system's acoustics and use the fan cable if desired to lower system level acoustics.

W

STATUS:

NoFix. PIO IDE mode 3 drives causes no boot condition

11.

PROBLEM: The STL2 server board will not boot with a PIO IDE mode 3 drive connected. Only PIO modes 0

and 4 IDE drives work with the STL2 server board.
IMPLICATION : W

PIO IDE mode 3 drives cannot be utilized with the STL2 server board.
: No workaround exists for this issue.

ORKAROUND

STATUS:

NoFix. SC5000 350 watt power supply fan failure not reported in the SEL

12.

PROBLEM: When a STL2 server board is installed in the SC5000 chassis, a 350-watt power supply fan failure

will currently light the front panel fault LED but there will be no corresponding system event log (SEL) entry for this failure. 8-94 Revision 1.1


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Errata Listing

IMPLICATION : SC5000 chassis 350-watt power supply fan failures will not be recorded in the STL2 server board SEL. W
ORKAROUND

: No workaround exists for this issue.

STATUS:

Fixed. This erratum has been fixed in STL2 FRU/SDR v. 4.3.6. Boot order issue with SCSI CDROM drives

13.

PROBLEM: The STL2 server board changes the boot order of an installed SCSI CDROM drive when a CDROM

is not loaded in the CDROM drive. The SCSI CDROM drive is moved to a bottom of the boot priority list in BIOS setup when the system is booted without a CDROM in the CDROM drive.
IMPLICATION : The customer may need to set the boot order of the SCSI CDROM drive in BIOS setup

prior to booting the system from a bootable CDROM, otherwise the system may not boot from the bootable CDROM.
ORKAROUND: Set the boot order of the SCSI CDROM drive in BIOS setup just prior to booting the system from a bootable CDROM.

W

STATUS:

Fixed. This issue is fixed in STL2 BIOS Release 1.4 (Build 18) and later versions. Three percent no boot failure following battery replacement due to Super I/O errata

14.

PROBLEM: Due to an erratum with the Super I/O PC97317 component, approximately three percent of STL2

server boards will not boot following user replacement of an expired battery.
IMPLICATION : When the battery is replaced on the STL2 server board following battery expiration, there is a

three percent chance that the board will not boot.
W
ORKAROUND

: No workaround exists for this issue.

STATUS:

Fixed. This issue has been fixed in STL2 BIOS Release 1.2 (Build 16) and later versions. Red Hat Linux 6.1 installation issue

15.

PROBLEM: The driver for the onboard Adaptec* AIC-7899 SCSI controller included in the Red Hat Linux 6.1

distribution does not load during the first part of the installation. The error message "SCSI HOST 0 ABORT TIMED OUT ­ RESETING" appears.
IMPLICATION : Difficulties installing Red Hat Linux 6.1on the W

STL2 server board may be encountered.

ORKAROUND: Red Hat Linux 6.2 SBE2 includes the correct drivers to allow normal installation. Install Red Hat Linux 6.2 or update the Adaptec drivers in Red Hat Linux 6.1.

STATUS:

Fixed. This erratum is fixed in Red Hat Linux 6.2 SBE2.

16. SC5000/SR2050 chassis HSC firmware update is not possible with the STL2 server board installed
PROBLEM: It is not possible to update the SC5000 or SR2050 chassis' HSC firmware with the STL2 server

board installed in the chassis. This is because the STL2 server board does not support an I2C interface connection between the server board and the chassis' hot swap backplane / SAF-TE card. The universal Revision 1.1 8-95


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versions of both the SC5000 and SR2050 chassis include the latest version of HSC firmware available. Any changes to the chassis HSC firmware will be made by incorporated by the ECO process.
IMPLICATION : It is not possible to update the SC5000 or SR2050 chassis' HSC firmware with the STL2 server

board installed.
ORKAROUND: It is possible to update the SC5000 or SR2050 chassis' HSC firmware with the L440GX+ server board ins talled. If a non-universal version of the SC5000 or SR2050 chassis requires an update to the HSC firmware, a L440GX+ board may be installed in the chassis in order to perform the HSC firmware update.

W

STATUS:

NoFix.

17. Red Hat Linux 6.2 SBE2 and 7.0 only recognize 64MB of memory with BIOS Release 1.2 and 1.3
PROBLEM: STL2 server boards programmed with BIOS Release 1.2 (Build 16) or BIOS Release 1.3 (Build 17)

running Red Hat Linux 6.2 SBE2 or 7.0 will recognize only 64 MB of the total installed memory, regardless of the actual memory size installed on the server board. Other operating systems recognize the total installed memory size.
IMPLICATION : Only 64 MB of the total installed memory will be recognized by Red Hat Linux 6.2 SBE2 or 7.0. W
ORKAROUND

: This issue does not exist when using STL2 BIOS Release 1.1 (Build 15).

STATUS:

Fixed. This issue is fixed in STL2 BIOS Release 1.4 (Build 18) and later versions. STL2 System Setup Utility does not allow display or modification of system IRQ mapping

18.

PROBLEM: The STL2 System Setup Utility (SSU) v. 1.R.1 does not contain an option to display or allow

modification of the system IRQ mapping.
IMPLICATION : STL2 server board system IRQ mapping information cannot be displayed or modified within the

SSU.
W
ORKAROUND

: If system IRQ modification is necessary, this can be done in the STL2 BIOS Setup utility.

STATUS:

NoFix.

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Glossary

Appendix A: Glossary
Term ACPI API APIC BDA BIOS BMC CMOS DIMM DMA DRAM EBDA ECC EMP ESCD FC -PGA FDC FIFO FRB FRU FSB ICH IDE I/O IPMI IPMB IRQ ISA LAN LED LSB LUN LVD MP MPS MSB MTBF NIC NMI Advanced Programmable Interrupt Intel Advanced Programmable Interrupt Controller Binary Data Area Basic Input Output System Baseboard Management Controller Complementary Metal-Oxide Semi-Conductor Dual In -Line Memory Module Direct Memory Access Dynamic Random Access Memory Extended BIOS Data Area Error Correcting Code Emergency Management Port Extended System Configuration Data Flip Chip Pin Grid Array Floppy Disk Controller First-In, First-Out Fault Resilient Booting Fi eld Replaceable Unit Front Side Bus I/O Controller Hub Integrated Device Electronics Input / Output Intelligent Platform Management Interface Intelligent Platform Management Bus Interrupt Request Industry Standard Architecture Local Area Network Light Emitting Diode Least Significant Bit Logical Unit Number Low Voltage Differential Multiprocessor Intel Multi -Processor Specification Most Significant Bit Mean Time Between Failures Network Interface Card Non-Maskable Interrupt Definition Advanced Configuration and Power Interface

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Term NRTL NVRAM OEM OS PCI PIC PIO PnP POST PTC PXE RAM RAMDAC ROM RTC RX SCAM SDRAM SDR SCSI SE SEL SGRAM SIO SMC SMI SMM SSU SVGA TX USB VCCP VRM WDT WOL ZIF

Definition Nationally Recognized Testing Laboratory Non-Volatile Random Access Memory Original Equipment Manufacturer Operating System Peripheral Component Interconnect Programmable Interrupt Controller Programmed Input/Output Plug-and-Play Power On Self Test Positive Temperature Coefficient Preboot Execution Environment Random Access Memory Random Access Memory Digital-to -Analog Converter Read Only Memory Real Time Clock A communications abbreviation for receive. Contrast with TX.

SCSI Configuration Automatically
Synchronous Dynamic Random Access Memory Sensor Data Record Small Computer Systems Interface Single Ended System Event Log Synchronous Graphics RAM Super I/O Satellite Management Controller Server Management Interrupt Server Management Module System Setup Utility Super VGA A communications abbreviation for transmit. Contrast with RX. Universal Serial Bus Voltage Controlled Current Plane Voltage Regulating Module Watchdog Timer Wake-on-LAN Zero Insertion Force

ii

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Glossary

Appendix B: Reference Documents
· · · · · · · · · · · · · · ·

5-Volt Flash File (28F008SAx8) Datasheet. Adaptec AIC-7899 PCI Bus Master Dual-channel Ultra160 SCSI Host Adapter Chip Data Book . Advanced Configuration and Power Interface Specification, Revision 1.0 AIC-7899 PCI-Dual Channel SCSI Multi-function Controller Data Manual. ATI Rage IIC Technical Reference Manual. I2C Bus Specification. Intel 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet. Intelligent Platform Management Bus Communications Protocol Specification. Intelligent Platform Management Interface (IPMI) Specification, Version 1.0. PCI Local Bus Specification, Revision 2.2. ServerWorks ServerSet* III LE North Bridge Specification. ServerWorks ServerSet* III LE South Bridge Specification. USB Specification, Revision 1.0. VRM 8.4 DC-DC Converter Specification. Wired For Management Baseline Specification, Revision 2.0
Á

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Index

Index
A
ACPI, 2-5, 3-21, 3-23, 3-24, 4-47, 5-71 Adaptec* AIC7899, 1 -1, 2-6 Address, 2 -7, 2-11, 2-15, 3-23, 4-37, 4-50 AIC -7899, 2-6, 2-7, 2-8, 2-18, 4-38, III APIC, 2-4, 2-8, 2-12, 2-13, 2-15 Architecture, 2 -3 ATI* Rage IIC, 2 -10, 2-11, 2-18, III

D
DC-to -DC converter, 2 -4 DIMM, 1 -1, 2-5, 4-32, 4-44, 4-49, 4-50, 5-55

E
ECC, 1-1, 2-5, 3-21, 3-22, 4-49, 7-77 EEPROM, 2-7 Emergency Management Port, See EMP, 3 -23, 4-49, 450, i EMP, 3-23, 4-49, 4-50, i Error, 3-21, 3-22, 3-23, 4-31, 4-32, 4-36, 4-44, 4-48, 4-49, 4-50, 4-51 ESM, See Enterprise System Management Console, 3 23 Ethernet, 1 -2, 2-8, III Exit Menu, 4 -27, 4-30, 4-38

B
Baseboard Management Controller See BMC, 1-2, 3-19, i BIOS, ii, 1-2, 2-6, 2-8, 2-12, 2-14, 2-15, 3-19, 3-21, 3-24, 4-25, 4-26, 4-27, 4-30, 4-32, 4-38, 4-39, 4-40, 4-41, 442, 4-43, 4-44, 4-45, 4-46, 4-48, 4-49, 4-50, 4-51, 4-53, 4-54, 5-58, 5-59 BIST, 3-22 BMC, 1-2, 2-3, 2-12, 2-14, 3-19, 3-21, 3-22, 3-23, 3-24, 449, 4-50, 4-51, 5-61, i Bridge, 1-1, 2-4, 2-5, 2-8, 2-12, 2-13, 2-15, 2-18, III Built -in Self Test See BIST, 3-22

F
Fan, 3 -21, 6-75 Fan, See also Sensor, Fan, 2 -4, 3-20, 3 -22 , 5-63, 5-71 Fan, System, 5 -63 Fault Resilient Booting, See FRB, 3-19, 5-61, i FC-PGA, 1-1, 2-3, 2-4 Field Replaceable Unit See FRU, 3-19, i Flash ROM, 4 -26, 4-39, 4-43 Flip Chip Pin Grid Array, 1-1, i FRB, 3-19, 5-61, i Front Panel, 3 -21, 3-22, 5-71 Front Panel reset, 3 -21, 3-22, 3-23, 4-32, 4-39, 4-45, 453, 5-71 Front Side Bus, 1 -1 FRU, 3-19, 4-49, 4-50, i

C
Certification, 7-78 Chassis Intrusion, 3 -20, 3-21, 5-57, 5-61, 5-71 Checksum, 4 -44, 4-50, 4-51 CMOS, 2-14, 4-25, 4-26, 4-27, 4-38, 4-39, 4-40, 4-41, 445, 4-46, 4-48, 4-49, 5-57, 5-58, 5-59 CMOS Clear Jumper, 5-57 Configuration, 2 -7, 2-11, 3-24, 4-26, 4-27, 4-29, 4-32, 433, 4-39, 4-50, 4-53, 5-56, 5-57, 5-61, i, III Connection, 3 -22, 4-37, 5-64, 5-67, 5-68, 5-69 Connector, Drive, 5 -64 Connector, Fan, 5 -63 Connector, PCI, 5 -69, 5-70, 6-75 Connector, Powe r, 5-62 Console Redirect, 4 -36, 4-37 Console Redirection, 4 -26, 4-36, 4-37 Controller, 1-2, 2-6, 2-7, 2-8, 2-10, 2-11, 2-13, 3-19, 4-33, 4-45, 4-48, 4-50, III

G
Glossary, i GPIO, 2-5

Revision 1.1

V


Index

STL2 Server Board TPS

I
I2C, 3-23, 5-62, III IB6566 South Bridge, 1 -1, 2-4, 2-5, 2-8, 2-12, 2-13, 2-14, 2-15, 2-18 ICH, 2-9 Initialization, 3-22, 3-23, 4-36, 4-51, 4-53 Install, 4-47 Intel® 82559, 1-2, 2-8, 2-9, 2-18, III Intel® CeleronTM processor, 2 -3 Intelligent Platform Management Bus See IPMB, i, III Interrupt Controller, 2 -13, 4-45 IPMB, 4-50, i, III IRQ 12, 2-18 ISA, 2-12, 2-13, 2-14, 2-15, 3-19, 3-22, 4-46

North Bridge, 1 -1, 2-5, 2-18, III NVRAM, 4-27, 4-38, 4-39, 4-49

P
Password, 3 -22, 4-35, 4-39, 4-49, 5-57, 5-58 Password Clear, 5 -57 PERR, 3-21, 3-22, 4-36, 5-69, 5-70 PGA370, 1-1, 2-3, 2-4 PIC, 2-13, 2-15, 2-16, 4-34, 4-48 POST, 3-21, 3-22, 3-23, 4-27, 4-28, 4-31, 4-32, 4-40, 4-41, 4-42, 4-44, 4-45, 4-47, 4-48, 4-50, 4-51, 5-58, 5-59, ii POST Code, 4 -44 Power Button, 3 -21, 3-22 Power Control, 3 -20 Power Distribution Board, 3 -20 Power Down, 3 -23 Power state, 3 -23 Power Supply See Sensor, Power Supply, 3 -20, 5-55 Power-on Self -Test See POST, 3 -21, 3-22, 3-23, 4-27, 4-28, 4-31, 4-32, 440, 4-41, 4-42, 4-44, 4-45, 4-47, 4-48, 4-50, 4-51, 558, 5-59, ii PXE, 3-21, 3-22, 3-23, 4-37

J
JEDEC, 1-1, 2-5

L
LED, 5-71 Legacy, 2 -13, 4-38 Logo, 4 -39 LUN, 4-53

R
Real Time Clock See RTC, 1-2, ii Recovery, 4 -43, 4-44, 4-48, 5-58, 5-59 Redirection, 4 -36 Reference Documents, III Reset Button, 3 -21, 3-23 RTC, 2-13, 3-24, 4-41, 4-49, ii

M
Magic Packet, 3 -20 Main Menu, 4 -27, 4-28, 4-29, 4-30 Management Controller See also FPC See also BMC See also HSC, 1-2, 2-14, 3-19, 4-49, 4-51 Memory, 2 -3, 2-5, 2-7, 2-11, 2-15, 3-21, 3-22, 4-32, 4-38, 4-49, 4-50, 6-75, ii Message, 4 -48 Modem, 4-37 MPS, 4 -26, 4-32 Multi-Processor Specification, See MPS, 4 -26, 4-32

S
SC242, 2-3 SC242 connector, 2 -3 SCSI, 1-1, 2-3, 2-6, 2-7, 2-8, 2-18, 3 -21 , 4-25, 4-26, 4-33, 4-34, 4-35, 4-39, 4-52, 4-53, 4-54, 5-56, 5-66, 5-67, 675, III SCSI Connector, 4 -52, 5-66, 5-67 SDR, 3-19, 4-49, 4-50, ii SDR Repository, 3 -19, 4-49, 4-50 SDRAM, 1 -1, 2-5, 6-75 Secure Mode, 3 -20, 3-22, 4-35, 4-36 SecureBIOS, 4-26 Security, 3 -20, 3 -22 , 4-26, 4-27, 4-29, 4-35

N
NB6635 North Bridge, 1-1, 2-5, 2-18 NMI, 3-21, 3-22, 4-36, 5-56, 5-71, i Non -maskable Interrupt, i

VI

Revision 1.1


STL2 Server Board TPS

Index

Processor, 2 -3, 2-4, 3-20, 3-21, 3 -22 , 3-24, 4-30, 4-31, 445, 4-46, 5-57, 5-59, 5-60, 5-63 SEL, 3-19, 3-21, 3-22, 4-50, ii Sensor, i i, 3-19, 3-20 Sensor Data Record, See SDR, 3-19, ii Sensor Event, 3 -19, 3-21, 3-22, 4-36, ii Sensor, Chassis Intrusion, 5 -56 Sensor, Fan, 2 -4, 3-20, 3 -22 , 5-63, 5-71 Sensor, Processor, 2 -3, 2-4, 3-20, 3-21, 3 -22 , 3-24, 4-30, 4-31, 4-45, 4-46, 5-57, 5-59, 5-60, 5-63 Sensor, Temperature, 3 -20, 3 -21 , 4-49 Sensor, Type , 3 -20 , 3-21 Sensor, Type Code , 3 -21 Sensor, Voltage, 3 -20, 3 -21 , 7-77, 7-79 Serial, 1-1, 1-2, 2-14, 4-31, 4-33, 4-37, 5-56, 5-65, ii SERR, 3-21, 3-22, 5-69, 5-71 Server Management, 3 -19, ii Serve r Menu, 4 -36 ServerWorks ServerSet III LE chipset, 1 -1, 2-3, 2-5 Setup Utility, 3 -24, 4-25, 4-26, 4-27, 4-28, 4-39, 5-58, ii SGRAM, 1-2, 2-8, 2-10, ii Shadow, 4 -45, 4-46, 4-47, 4-48, 4-49, 4-50 Shutdown, 4 -47 SMBIOS, 4-50 SMI, 3-19, 3-21, 3-23 SMM, 4 -43, ii South Bridge, 1 -1, 2-4, 2-5, 2-8, 2-12, 2-13, 2-15, 2-18, III Speaker, 5 -63 SSU, 4-25, 4-27, ii Super I/O Controller, 1 -2 System Event Log, See SEL, 3-19, 3-21, 4-36, ii System Management Software, 3 -19 System Setup Utility, See SSU, 4-25, 4-27, ii

termination circuitry, 2 -4 Third -party instrumentation, 1 -1, 2-6, 2-18, 4-52, 4-53, 4-54, III Timeout, 3 -21, 3-22, 3-23 Transfer Mode, 4 -31 Type Code See also Sensor, Type Code , 3 -21

U
Ultra160 LVD, 5-56 Universal Serial Bus, 1 -1, 1-2, 2-5, 2-8, 2-12, 2-13, 2-15, 4-33, 4-46, 5-56, 5-66, 6-75, ii, III USB, 1-1, 1-2, 2-5, 2-8, 2-12, 2-13, 2-15, 4-33, 4-46, 5-56, 5-66, 6-75, ii, III User Binary, 4 -42, 4-43

V
Voltage, See also Sensor, Voltage, 3 -20, 3 -21 , 7-77, 779 VRM, 1-1, 2-4, 5-55, 6-74, 6-75, III

W
Warning, 4 -50 Windows NT, 3 -24, 6-75

Z
zero -insertion force socket, 2 -3, 2-4 ZIF socket, 2 -4

T
Temperature, See also Sensor, Temperature, 3 -20, 3 21 , 4-49

Revision 1.1

VII